-
ds1302_seg7
使用Verilog完成DS1302的驱动,工程已经经过测试,可直接使用。(DS1302 using Verilog complete drive, the project has been tested and can be used directly.)
- 2014-12-10 15:27:48下载
- 积分:1
-
用VHDL语言仿真音乐设计
用VHDL语言仿真音乐设计
用VHDL语言仿真音乐设计
用VHDL语言仿真音乐设计-Simulation using VHDL language music design music design simulation VHDL language
- 2022-06-30 21:47:10下载
- 积分:1
-
eeprom
I2C EEPROM 存取源碼, 通用ATMEL(I2C EEPROM read/write)
- 2012-09-19 19:59:12下载
- 积分:1
-
控制ADV212 压缩的源代码 使用xilinx edk开发环境
控制ADV212 压缩的源代码 使用xilinx edk开发环境(adv 212 controller, using xilinx edk)
- 2020-06-27 03:40:01下载
- 积分:1
-
Array-multiplier
Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs
- 2015-02-21 12:59:12下载
- 积分:1
-
keyscan
用verilog语言写的简单的键盘扫描代码,适合初学者,用alter的软件编写的程序代码。(Using verilog language to write simple keyboard scan code, suitable for beginners, with alter software program written code.)
- 2013-09-13 22:59:11下载
- 积分:1
-
本程序实现不同频率时钟的产生及其相互转化
本程序实现不同频率时钟的产生及其相互转化-this program different clock frequencies to the formation and transformation
- 2022-03-06 09:31:43下载
- 积分:1
-
主要是通过Altera公司的Cuclone系列的FPGA
主要是通过Altera公司的Cuclone系列的FPGA-EP1C3T144C8产生余弦波的源代码 基于LPM-ROM余弦波一周期含有256个10位数据;-Mainly through Altera s Cuclone series of FPGA-EP1C3T144C8 cosine wave generated source code based on the LPM-ROM cosine wave of one cycle containing 256 10-bit data
- 2023-06-17 01:00:03下载
- 积分:1
-
UART(RS232)
用VERILOG语言实现的通用异步串行收发器(RS232收发器),波特率可设置,通讯稳定,已成功应用于实际项目。(VERILOG language with universal asynchronous serial transceivers (RS232 transceiver), the baud rate can be set, communication stability, has been successfully applied in actual projects.)
- 2021-04-01 10:59:08下载
- 积分:1
-
verilog HDL语言,对于超大规模集成电路开发学习非常有好处
verilog HDL语言,对于超大规模集成电路开发学习非常有好处-verilog HDL language, for ultra-large-scale integrated circuits are very beneficial to the development of learning
- 2022-12-28 13:40:09下载
- 积分:1