30 vhdl source for the beginning of the study vhdl helpful, and can help to unde...

基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)

Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)

This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery.

有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)

least mean square algo implemented on verilog

ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules

收集的QuartusII的使用手册，包含了几个pdf文件，比较不错的参考手册-Collected QuartusII s manual contains a number of pdf files, compare a good reference manual

以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)

基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE(RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE)

说明：  写出13个简单的Verilog demon，适合初学者观摩学习。配合实验报告，食用更佳。(Write 13 simple Verilog demon, suitable for beginners to observe and learn. With the experimental report, it is better to eat.)