The use of ip core

说明：  用于实现FPGA硬件开发使用的加法器，需要注意的是用Verilog语言实现的(The adder used to realize FPGA hardware development needs to be realized in Verilog language)

应用在电机上的svpwm代码，Verilog编写，已经测试成功

说明：  fpga版本的数码管动态扫描程序，可供学习(FPGA version of the digital tube dynamic scanning program for learning)

摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。 关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ(Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ)

CSC RGB2YUV Verilog source code

SERDES资料，包括reliability_handbook,serdes_handbook,serdes_introduction(SERDES doc,include reliability_handbook,serdes_handbook,serdes_introduction)

de2-70 camera 亲测可以下载验证 直接下载使用即可

说明：  数电实验FPGA verilog代码，包括秒表、全加器、半加器等。(FPGA Verilog code for digital experiment)

VHDL 源码模块，可以实现最经典原PWM，可以用于电源，电机的控制()

伺服电机主控制模块输入输出特性的简单模拟实现，输入目标电压及反馈的当前电压，输出对电机的控制脉冲波形(The simple simulation of the input and output characteristics of servo motor main control module, the input is target voltage and feedback is the current voltage, the output is the motor control pulse waveform)