zybo1_FPGA_Design_Flow_using_Vivado

module example_3_1(A, B, C, D, E);        output D, E;    input  A, B, C;    wire   w1;    and G1(w1, A, B);    not G2(E, C);    or  G3(D, w1, E); endmodule

说明：  ddr2原理图设计，原厂电路图设计，很好很强大 16bit(ddr2 schematic design, the original schematic design, a very powerful 16bit)

ADC Reference code!Clock 100kHz

用VERILOG实现 交通灯控制，且运行正确，希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)

按键控制数码管显示，从0到9显示，八位数码管(Button control digital tube display)

fpga通过usb 向电脑发送计数器的数据  程序亲测可用

基于FPGA和matlab设计的IIR滤波器，利用matlab的simulink工具进行设计，包含了源码和相关文档说明，希望能够对大家有所帮助

fifo异步串口收发程序 FPGA程序(fifo asynchronous serial transceiver)

一个精确时钟的v-log程序，只用一个全局时钟，增加了精确度(An accurate clock in the v-log program, only one global clock, increased accuracy)

GPS 导航器TFT 驱动源程序。主CPU为ATmel的AT91sam9261（ARM926的内核）(TFT GPS navigation device driver source code. CPU for the AT91sam9261 ATmel (ARM926 the kernel))