VHDL实现二维DCT变换

fpga的一个小程序用于3s500e 4*4键盘模块(fpga is a small program used 3s500e 4* 4 keyboard module)

verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."

3X3矩阵乘法的VHDL程序实现！对初学者有很大的帮助！-3X3 matrix multiplication VHDL program! For beginners is a great help!

本例是关于卷积码的一个简单算法，用verilog HDL语言编写，整个文档包括了产生卷积的整个工程。-In this case is a convolutional code on a simple algorithm, using verilog HDL language, the entire document, including the method of deconvolution of the whole project.

这是我自己编写的三分频，也就是奇数分频，占空比为1：1，当然如果需要其它奇数分频，只要将程序里面的N和counter修改即可-This was my third prepared by the frequency, which is odd hours, frequency and duty ratio of 1:1. Of course, if the needs of other odd hours, frequency, as long as the proceedings inside the N and counter can be amended

TFT 液晶屏显示，通过按键，显示不同的曲线(TFT LCD display)

基于fpga的实时视频采集与显示 高速化 小型化-fpga

电子书籍 verilog HDL 数字设计与综合 夏宇闻所编写(electronic text Foreign electronic and communication textbooks)

使用uaf42设计的有源滤波器，高通滤波器的设计参数记录(Using uaf42 design active filters, high-pass filter design parameters recorded)

此功能是实现曼彻斯特编码的Verilog代码，经过在xilinx sp6上实际运行证实可行。(This function is to achieve the Manchester code Verilog code, through the Xilinx SP6 actual operation proved.)