Xilinx

锡林克斯巴达官方文件有详细说明，支持斯巴达、顶点

Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)

主要介绍，I2C总线主设备发送数据给从设备，代码实现是用Verilog语言实现的，对硬件设计者有很大好处(Introduces, I2C bus master to send data to the slave device, code is implemented in Verilog language, the hardware designer of great benefit)

本RAR包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。(The RAR includes " Verilog-HDL Practice and Application of system design," a book full of examples, all passed validation. Chapter VII of the future design examples, not only examples of Verilog-HDL, but also attached, including VB, VC++ source code, etc., and even DLL generation methods explained in detail.)

基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控(Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable)

波形发生器，用于编写testbentch文件。非常实用-Waveform generator, for the preparation of testbentch files. Useful

program in hdl that this open mind in digital resources

使用两个8点FFT完成64-point FFT(64-point FFT)

turbo码的编码程序,verilog HDL,在ISE环境中(turbo code encoding process)

CAN VHDL Code. Behavioral implementation of CAN bus interface.