vhdl编的dds函数发生器，完成sin(x)曲线的生成

基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来(Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it)

MODELSIM的实验程序，在QUARTUSii中调用MODELSIM，实现仿真-ModelSim Experimental procedures QUARTUSii call MODELSIM, realize Simulation

win10的xilinx usb驱动，较新版本(Xilinx USB driver for win10, newer version)

说明：  希望对VHDL的学习大家有帮助，望大家指出错误，浮想交流！(We want to learn VHDL help, hope you point out an error, daydreams exchange!)

VHDL 编写的RAM例子-RAM prepared VHDL example

1对于按键输入，请加入语音输出电路，代表按键sw1反馈的音频信息。每次按下sw1按钮时，它们都会发出0.1秒1KHz的声音。

在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)

如果需要用verilog设计一项比较简单的功能，那么这个浅显易懂的程序能让你很快明白点阵的设计方法，尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)

本书作者为夏宇文，详细讲解了从算法设计与验证到硬件逻辑实现的过程，要求读者有一定的verilog基础(This book author XIA Yu-Wen gave a detailed account from algorithms to hardware logic design and verification of implementation process, requiring readers to have some basis for verilog)

说明：  Ovo sto saljem je tutorijal 7 sa vhdlom