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CHANNEL_ESTIMATION_PROJECT
基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来(Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it)
- 2013-04-22 19:29:00下载
- 积分:1
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MODELSIM的实验程序,在QUARTUSii中调用MODELSIM,实现仿真
MODELSIM的实验程序,在QUARTUSii中调用MODELSIM,实现仿真-ModelSim Experimental procedures QUARTUSii call MODELSIM, realize Simulation
- 2022-04-13 16:01:45下载
- 积分:1
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xilinx_usb_drivers_win10_x64
win10的xilinx usb驱动,较新版本(Xilinx USB driver for win10, newer version)
- 2021-03-11 17:09:26下载
- 积分:1
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shiyanc
说明: 希望对VHDL的学习大家有帮助,望大家指出错误,浮想交流!(We want to learn VHDL help, hope you point out an error, daydreams exchange!)
- 2011-04-14 09:10:28下载
- 积分:1
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VHDL 编写的RAM例子
VHDL 编写的RAM例子-RAM prepared VHDL example
- 2023-03-23 05:20:03下载
- 积分:1
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1. For the key input, please join the voice output circuit, representing the key...
1对于按键输入,请加入语音输出电路,代表按键sw1反馈的音频信息。每次按下sw1按钮时,它们都会发出0.1秒1KHz的声音。
- 2022-03-02 14:32:00下载
- 积分:1
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DDR3_user_design
在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器,里面生成了Core,可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)
- 2012-02-02 15:16:00下载
- 积分:1
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dianzhen
如果需要用verilog设计一项比较简单的功能,那么这个浅显易懂的程序能让你很快明白点阵的设计方法,尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)
- 2014-01-16 16:13:53下载
- 积分:1
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algorithm_design_and_logic_implemention
本书作者为夏宇文,详细讲解了从算法设计与验证到硬件逻辑实现的过程,要求读者有一定的verilog基础(This book author XIA Yu-Wen gave a detailed account from algorithms to hardware logic design and verification of implementation process, requiring readers to have some basis for verilog)
- 2009-11-11 21:19:03下载
- 积分:1
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Tutorijal 6
说明: Ovo sto saljem je tutorijal 7 sa vhdlom
- 2018-12-22 06:47:31下载
- 积分:1