vhdl编的dds函数发生器，完成sin(x)曲线的生成

本程序是用verilog 编写的模块，用来在lcd1602上显示用tlc549采样的电压值(This program is written in verilog module, used in lcd1602 display with tlc549 sampled voltage value)

generate sine wave. Inputs : Amplitude, phasein, frequency

一个在CPLD，EPM70128上实现的PWM控制源程序。(A CPLD, EPM70128 realize the PWM control on the source.)

硬件设计vhdl_cpu1,1. You may copy and distribute verbatim copies of this core, as long -- as this file, and the other associated files, remain intact and -- unmodified. Modifications are outlined below.-hardware design vhdl_cpu1, 1. You may copy and distribute verbatim copies of this core, as long-- as this file, and the other associated files, remain intact and-- unmodified. Modifications are outlined below.

高速双端口RAM的vhdl实现。包含仿真波形-High-speed dual-port RAM realize the VHDL. Contains the simulation waveform

在学习verilog 中与遇到一些列问题的整理。(this Documentation is about the problem about verilog which is meeted when i was learn FPGA)

verilog实现基于i2s协议接口，在fpga上验证通过。(Verilog implements the interface based on I2S protocol and verifies it on fpga.)

说明：  一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。(A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.)

这是基于Quartus2 开发环境和verilog hdl语言写的38译码器(This is based development environment and Quartus2 verilog hdl language used to write decoder 38)

递增方式在4位数码管上向上计数显示从0000-0001->0002……..9999….0000….0001…. -- 利用CPLD设计了一个4位十进制计数器，并用数码管显示当前计数值-Incremental approach in the four counts upward digital tube display from 0000-0001-