SMII 到 MII 转换的VHDL代码

交织器主要是对输入数据按照一定的规则打乱以便减少数据中过长的连0或者连1的出现。交织矩阵为行列矩阵，msgin为输入比特，msgout为交织输出比特，row和rol为交织器的行和列，可以通过改变col改变交织深度。先把输入的比特流数据改变为一个矩阵，再按照一定的方式输出为比特流数据

HDLC接口协议的FPGA实现使用verilog-design of HDLC

　M4A564/32 CPLD VHDLＡ程序，调试可用,51扩展.-M4A564/32 CPLD VHDLA procedures, debugging is available, 51 to expand.

基于verilog的FFT设计，使用vivado作为开发平台(Verilog based on the FFT design, the use of vivado as a development platform)

Xilinx ISE 8.2i的license-Xilinx ISE 8.2i s license

开发环境：maxplus2 a/d convortor-development environment : maxplus2 a/d convortor

接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated data The compressed package includes the Verilog code, the testbench code Matlab simulation code)

开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit

VGA显示彩条DE2_70开发板 验证过的(VGA display color bar DE2_70 development board validated)

read data of type character from flash memory