SMII 到 MII 转换的VHDL代码

液晶显示屏显示汉字“年”的驱动程序VHDL(nian VHDL)

基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)

先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。(First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.)

用ALTERA的FPGA实现UDP通信源代码(FPGA UDP)

说明：  自适应滤波器算法LMS ，的FPGA实现，采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)

说明：  FPGA和双端口RAM的DDS任意波形发生器的实现(FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator)

用状态机实现密码锁State machine used to achieve code lock-State machine used to achieve code lock

设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter

dac714的控制程序，包括spi数据通信，转换控制(dac714 control procedures, including the spi data communications, switching control)

Modelsim+DC开发的4级流水线结构的MIPS CPU(mips 4level cpu)