登录
首页 » VHDL » SMII 到 MII 转换的VHDL代码

SMII 到 MII 转换的VHDL代码

于 2023-06-26 发布 文件大小:5.24 kB
0 178
下载积分: 2 下载次数: 1

代码说明:

SMII 到 MII 转换的VHDL代码-SMII to MII conversion of VHDL code

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • bit7_Binary_to_BCD_LED
    二进制转十进制BCD码 Verilog语言 quartusII(Binary to decimal BCD code Verilog language quartusII)
    2013-09-14 16:49:39下载
    积分:1
  • usb2lpt
    German REAL LPT! USB2LPT
    2012-08-05 03:33:40下载
    积分:1
  • Lesson1
    FPGA课件,个人感觉不错,希望对大家有帮助(FPGA software, personal feel good, I hope all of you help)
    2009-06-13 10:27:35下载
    积分:1
  • loop
    对锁相环路的仿真,二阶环的仿真与分析都可以通过这个文件来到完成(Simulation of PLL, second-order loop simulation and analysis can be completed by the adoption of the document came)
    2008-12-17 23:00:35下载
    积分:1
  • Amp-diagrams_pack
    Diagram and how-to-make instructions pack of 6 diferent Amplifiers
    2010-10-24 18:40:43下载
    积分:1
  • sht30
    温湿度传感器sht30驱动,系统时钟为125M可读出温湿度。(sht30 driver,sysclk=125MHZ)
    2020-09-28 17:07:44下载
    积分:1
  • DecimationFilterDesignforDDCandImplementingItwithF
    本文介绍了在数字下变频(DDC) 中的抽取滤波器系统设计方法和具体实现方案。采用CIC 滤波器、HB 滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性(This article describes the digital down conversion (DDC) of the decimation filter system design methods and concrete realization of the program. Using CIC filter, HB filter, FIR filter cascade three-level approach to reduce the sampling rate. Through the actual authentication, to prove the feasibility of the design)
    2008-04-14 11:02:00下载
    积分:1
  • sqrt_pipeline
    说明:  Matlab - to hdl code for square root
    2020-06-17 12:20:02下载
    积分:1
  • crc_verilog_xilinx
    crc校验,非常好用,是从Xilinx的IP演化来的(crc脨 拢 脩茅 拢 卢 脟 鲁 拢 潞 脙脫脙 拢 卢 脢脟)
    2021-03-01 11:49:34下载
    积分:1
  • fpga
    说明:  中科院FPGA的课件!纯英文,比较简单,适合刚刚接触FPGA的小白!(Chinese Academy of Sciences FPGA courseware! Pure English, relatively simple, suitable for Xiaobai who just came into contact with FPGA!)
    2020-03-19 14:19:16下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载