DDR3 SDRAM con

说明：  基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)

开关数据加载到寄存器并显示的设计与实现.3． 设计一个可以把4个开关的内容存储到一个4位寄存器的电路，并在最右边的7段显示管上显示这个寄存器中的十六进制数字。我们使用到去抖动模块clock_pulse， 用btn[0]作为输入；8位寄存器模块，用btn[1]作为加载信号；7段显示管上的显示模块x7segbc；分频模块clkdiv，用以产生模块clock_pulse和x7segbc的clk190时钟信号。(Design of switching data is loaded into the register and display the.3. design and implementation of a 4 switch content storage circuit to a 4 bit register, and in the 7 section of the most on the right shows the register in the sixteen decimal digital display tube. We used to go to the jitter module clock_pulse, with btn[0] as the input 8 bit register module, as the loading signal by btn[1] 7 segment display module on the x7segbc pipe frequency module clkdiv, clk190 clock signal for generating module clock_pulse and x7segbc.)

资源描述本文讲的是基于FPGA的模糊PID控制器实现,详细介绍了Verilog HDL怎样用FPGA实现PID控制器

在FPGA开发平台上，通过按键控制一个弹球小游戏。输出VGA显示信号输送到显示器上显示(On the FPGA development platform button control of a pinball game. VGA output signal is supplied to the display displayed on the display)

将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)

这个项目是一个基于FPGA的alexnet第一卷积层实现。(This project is a FPGA based implementation of first Convolutional Layer of AlexNet.)

通过FPGA实现整数阶混沌系统，通过定点数的方式，全并行。(The realization of integer order chaotic systems through FPGA)

利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)

8位crc的verilog设计 通过仿真综合验证并已应用在工程里面 (verilog of 8bit error checkout )

Complete Successive approximation Analog to digital converter along with the source code