FPGA控制步进电机的Verilog程序

控制电话信令 完成忙碌 等待 回铃音振铃等(Signaling complete control over telephone ring so busy waiting ringback tone)

设计一个能求出一个32bit字中两个相邻0之间最大间隙的电路。完成HDL设计及testbench描述，给出综合后的时序仿真结果。提交纸质文档。(Design a circuit that can find the maximum gap between two adjacent 0 in a 32bit word. The HDL design and testbench description are completed, and the result of comprehensive simulation is given. Submit paper documents.)

编码器信号的转换，用于控制打印机，UV平板打印机的喷头驱动输出信号，控制Y轴移动，需要将信号转换为运动控制器识别的信号才可以控制其运动。

Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计(quartusII mips pipeline 32bit cpu design)

A programming language that can decode alpha numeric

基于ISP的交通灯设计，实现了各路状态转换、警察控制、行人请求功能。(ISP traffic light design, to achieve the brightest state transitions, police control, pedestrian request feature.)

基于Verilog的小波滤波器程序设计的总结文档。(Verilog based wavelet filter program design summary document.)

适用于Altera FPGA Nios II平台uClinux OpenCV之BmpDecoder的源码(Souce code of BmpDecoder for Altera FPGA Nios II uClinux OpenCV)

说明：  verilog语言书写，单周期CPU源码(single period CPU)

FPGA入门系列实验教程——实验四.LED跑马灯(Getting Started with FPGA tutorial series of experiments- Experiment IV. LED Marquee)