AHB总线相关协议代码

 RSA算法的描述 选取长度应该相等的两个大素数p和q，计算其乘积：                         n = pq 然后随机选取加密密钥e，使e和（p–1）（q–1）互素。 最后用欧几里德扩展算法计算解密密钥d，以满足                 ed = 1（mod（p–1）（q–1）） 即             d = e–1 mod（（p–1）（q–1）） e和n是公钥，d是私钥  

verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)

ahb总线Verilog代码及sv仿真文件(ahb bus Verilog code and sv simulation code)

硬件描述语言相关芯片程序源码Chip hardware description language-related program source code(Chip hardware description language-related program source Chip hardware description language-related program source code)

实现AHB转SRAM接口实现，支持猝发，零等待延迟(Implementation of AHB to SRAM Interface)

it contains pdf file which has vhdl program of uart (universal asynchoronus receiver and transmitter). which very simple and easy to understand

华为文档《硬件描述语言Verilog基础》-目录 原来搞VHDL，刚刚开始学Verilog。觉得这个入门的提纲不错，共享一下。 (Huawei Documents " basic Verilog Hardware Description Language" - the original directory engage in VHDL, just beginning to learn Verilog. Feel that the entry of the outline of a good, share some.)

6264是一种8K×8的静态存储器.SRAM 的典型芯片有2KB 的6116、8KB 的6264 以及32KB的62256,其中6264 芯片应用最为广泛.(6264 is the 62256 typical chip SRAM.SRAM a 8K* 8 with 2KB 6116, 8KB 6264 and 32KB 6264 chip, which is most widely used. )

用case 语句描述的4 选1 Mux 源码程序，好用(-4 with a case statement described 1 Mux source program, easy to use)

ad7705通过spi时序进行读写，通过fpga模拟spi时序对adc进行读写，首先写入通信寄存器20h，时钟寄存器0C，通信寄存器10，设置寄存器40H，然后写通信寄存器进行读取。