AHB总线相关协议代码

Commponent for drivering EEPROM memory AT25320 from Avalon bus.

说明：  本代码完成了一位数的加减法运算，并实现了在LED屏幕上的显示操作过程(This code completes the addition and subtraction operation of one digit, and realizes the display operation on the LED screen)

DE2-70开发板中附带的控制面板，可以读取存储器中的数据，这个可以正常连接和读取，有好几版本的，有的不能用，而这个经过我亲自测试。(DE2-70 development board comes with a control panel, you can read the data in the memory, this can be properly connected and read, there are several versions, and some can not be used, and this after I personally tested.)

使用verilog语言，滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)

此代码基于cyclone III开发。通过一排LED充当乒乓球，模拟打乒乓的游戏

SMbus通讯协议的Verilog程序段，已通过Moldesim的仿真，可用(Verilog program segment of the SMbus communication protocol, has been through the Moldesim simulation, the available)

在FPGA上用Verilog实现的UART串口通信模块，包含分频模块，接收模块，发送模块，可以更改波特率，适合初学者学习，已经在板子上得到了验证。

说明：  功能是（用Verilog语言的，内有比较详细的注释）： （1）计数器的功能是从0到9999计数，并能以十进制数的形式在七段数码管上显示出来(包括七段数码管显示模块). （2）该计数器有一个1个nclr和一个adj_plus端，在控制信号的作用下（见下表），计数器具有复位、增或减计数、暂停的功能。编写以上的程序的完整模块. 计数器的功能表 nclr adj_minus 功 能 0 0 复位为0 0 1 递增计数 1 0 递减计数 1 1 暂停计数 (Function is (with Verilog language, the more detailed comments): (1) counter function is from 0 to 9999 counts, and are able to form a decimal number on the seven-segment LED display (including the seven-segment LED display module). (2) The counter has a one nclr and a adj_plus side, under the action of the control signal (see below), the counter has reset, increase or decrease of count pause function. Complete the preparation of the above program modules. Counter function menu nclr adj_minus reset 0 0 0 0 1 1 0 counts counting suspended Count 1 1)

// DEFINES `define BITS 32         // Bit width of the operands `define NumPath 34        module bgm(clock,  reset, sigma_a,  sigma_b,  sigma_c, Fn, dw_x, dw_y, dw_z, dt, Fn_out  ); // SIGNAL DECLARATIONS input clock; input reset; input [`BITS-1:0] sigma_a; input [`BITS-1:0] sigma_b; input [`BITS-1:0] sigma_c; input [`BITS-1:0] Fn; input [`BITS-1:0] dw_x; input [`BITS-1:0] dw_y; input [`BITS-1:0] dw_z; input [`BITS-1:0] dt;

VERILOG HDL pid算法 带仿真验证(pid by verilog HDL)