SPI主/从

无线通信中接收侧自动增益控制模块的vhdl代码实现(Receive side of the AGC module vhdl code for wireless communications)

说明：  DDS的基本原理主要由五部分组成，分别是；相位累加器，正弦波形存储器，数模转换器，低通滤波器和时钟，将相位累加器输出的数据作为地址，用来查询表的数据，将取出的正弦数据通过数模转换器输出模拟信号，模拟信号再通过一个低通滤波器输出纯净的正弦波信号。(The basic principle of DDS is mainly composed of five parts: phase accumulator, sinusoidal waveform memory, digital to analog converter, low-pass filter and clock. The output data of phase accumulator is used as address to query the data of table. The extracted sinusoidal data is output analog signal through digital analog converter, and the analog signal is output pure sine through a low-pass filter Wave signal.)

同步 FIFO 的 Verilog 设计代码。核查 Env 可以围绕它 SV 或 UVM。数据宽度是 8 位和 FIFO 深度是 2 ^3 = 8

VHDL语言编写的I2C通信接口,可与单片机等MCU相连,只占用很少的引脚线完成数据的传输(Written in VHDL I2C communication interface, such as MCU and MCU can be connected, only takes a few lines to complete the data transmission pin)

说明：  一个小寄存器堆，使用参数化编程，附有仿真代码，可直接在vivado（2018.2版本及以后）上运行(A small register heap, using parametric programming)

通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made ​ ​ into a single-chip digital clock program)

基于FPGA的PAL_VGA转换器的实现.pdf(FPGA-based PAL_VGA converter implementation)

利用FPGA实现与powerpc的localbus数据接口代码。用verilog实现(localbus interface with PowerPC using Verilog)

文件描述的是SDH 指针处理和系统同步代码 veriolg(SDH pointer processing and system synchronization code veriolg of file Description)

利用ISE本身的IP核，实现GMII的网络传输，在ML605开发板上调试过，可以跑，有兴趣的可以看看，相互学习嘛