锁相环LMX2531的verilog配置程序

完整的GMSK调制及维特比译码，程序中包括了高斯滤波器的设计，调制相位的计算，并采用了维特比译码算法解调出原始码元，最后计算了其误码率。(Complete GMSK modulation and Viterbi decoding, the program includes a Gaussian filter design, the calculation of the phase modulation, and uses the Viterbi algorithm demodulates the source element, the final calculation of the bit error rate.)

这是一个很好的基于verilog的串口通信422模块，已经经过多次验证，绝对可靠，可直接使用，本人已在工程中多次使用，无误差(This is a good serial communication based on Verilog 422 module, has been repeatedly verified, absolutely reliable, can be used directly, I have repeatedly used in the project, no error)

xilink DPD V6.0 IP Core design example

关于LDPC解码的verilog程序，包含设计代码和验证环境(LDPC decoding on verilog procedures, including the design code and verification environment)

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)

VGA的verilog实现，通过宏控制输出格式，兼容altera的avalon总线。

基于数码管独立显示和三色灯的交通指示系统设计(Design of Traffic Indicator System Based on Digital Tube Independent Display and Tri-color Lamp)

32位存储器Verilog附带test文件，可以在modulesim仿真 还有加法、减法器，译码器等常用Verilog器件，都附带仿真test。(Memory test with Verilog)

cic设计 verilog verilog(cic verilog design verilog)

verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器(verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter)