一个简单的曼彻斯特编码器，将串行数据转换为曼彻斯特编码数据。

dp_xiliux 的 CPLD Verilog设计实验,流水灯演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, water lamp demonstration. code test.

de2 vga控制器，也可用于其他板子开发-de2 vga controller board can also be used for other development

HDLC接口协议的FPGA实现使用verilog-design of HDLC

AES TSAPI Retrieve Event in Non-blocking Mode

能够完美产生数字地面电视（DTMB）的信源的程序。帧头模式为模式一。信道可选择，信号加入频偏，延时，后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)

基于QuartusII环境下的地铁自动售票系统(Subway auto ticketing system based on QuartusII)

FPGA中实现的硬件UDP 协议 FPGA中实现的硬件UDP 协议

清华大学电子课程设计：Verilog，QuartusII可正确运行，可下载到FPGA上，完成远程通信的整体任务，PC发数据，键盘输入运算符与运算数计算将结果显示在数码管上并返回给PC机，需异步串口调试软件(Verilog, QuartusII run correctly, can be downloaded to the FPGA, to complete the overall task of remote communication, PC send data, keyboard operators and operands calculation displays the results in digital tube and returned to the PC, to be asynchronous serial debugging software)

实现beep发出1234567的音乐声音-beep 123456

该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐 (The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)