FSK信号发生器，基于VHDL语言，好用的！

FPGA／CPLD技术是近年来计算机与电子技术领域的又一场革命。本书以Xilinx与Altera公司的FPGA／CPLD为主，详细介绍了FPGA／CPLD从芯片到MAX+plusⅡ、Quartus与ISE开发环境和Verilog／VHDL语言，并以交通灯逻辑控制、电子钟与点阵LED显示、LCD液晶显示及计算机ISA接口和PCI接口的设计等为例，由浅入深地详述了如何应用FPGA／CPLD进行电子设计。书中的大多数电路图和源程序已经过实例验证，读者可以直接应用于自己的设计。本书的特点是强调实用性和先进性，力求通俗易懂。 本书适用于计算机、电子、控制及信息等相关专业的在校大学生，对广大工程技术人员也具有实用价值。(FPGA/CPLD technology in recent years the field of computer technology and electronic another revolution. Book Xilinx and Altera' s FPGA/CPLD based, detailing the FPGA/CPLD from the chip to MAX+plus Ⅱ, Quartus and ISE development environment and Verilog/VHDL language and logic control traffic lights, electronic bell with dot matrix LED display , LCD liquid crystal display and computer ISA interface and PCI interface design, for example, progressive approach to detail how the application of FPGA/CPLD for electronic designs. Circuit and the source of most of the book have been instances of verification, the reader can be directly applied to their own design. Characteristic of this book is to emphasize the practical and advanced, best straightaway. This book applies to computers, electronics, control and information and other related professional college students, the majority of engineering and technical personnel also has practical value.)

此文件给出了一个多功能交通灯的VHDL代码实现，可作为电赛的准备材料-This paper gives a multi-functional traffic lights to achieve the VHDL code can be used as electric materials Cup preparations

一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)

verilog编写的流水线模块-Verilog modules prepared by the Pipeline

基于FPGA的pci总线接口设计。。。。。。。。。。。。。(FPGA-based PCI bus interface design)

这是一个简单的定时器模块使用计数器

应用背景此代码是用于执行器和传感器，可以在网络中实现一个很好的连接与其他节点和主。关键技术VHDL代码 ；可以控制位CRC校验和填料-掩模的验收规范

说明：  这是32位移位寄存器，是用verilog编写的，能够实现从1到31位的左或右的移位(This is a 32-bit shift register, is prepared verilog, can be realized from the 1-31 shift left or right)

基于FPGA的温度计源代码，VHLL语言-Thermometer-based FPGA source code, VHLL language

定时器的编程，vhdl语言，可以实现24时制定时器-Timer programming, vhdl language, can be achieved when the system timer 24