ECC的Verilog代码

同步fifo，本设计采用同步fifo方式，中间例化ram，实现同步fifo传输

通过设置串口的波特率、起始位、检验位等参数，进行FPGA的串口通讯(By setting the baud rate, the starting bit, the test bit and other parameters of the serial port, the serial communication of FPGA is carried out)

adder 18b trong chuong trinh verilog

用verilog语言详细编写的源代码及顶层文件，含有时序图分析。要求有Quartus2开发环境。

台湾IC中心VHDL讲义，内容详细，适合IC前端设计参考(Taiwan s IC Center VHDL handouts, detailed reference design for front-end IC)

一个AXI slave的Verilog实现代码，内部有基于UVM编写的testbench,该slave是基于AXI3协议来实现的，可以给初学者一些启示

it contains pdf file which has vhdl program of uart (universal asynchoronus receiver and transmitter). which very simple and easy to understand

verilog编写的4端口驱动lcd1602，一般的都是8端口驱动，我的开发板是spartan3e的上面的lcd1602是死端口驱动的，当时找了各种资料才自己琢磨出来的，上传出来供大家参考一下！

说明：  八相移键控调制的Verilog程序，给出了各个子模块的程序，实现了信号调制。(Eight-phase shift keying modulation of the Verilog program, each module is given the procedures, the signal modulation.)

AGC(自动增益放大) Verilog代码 设计可以参考 第二部分(AGC (automatic gain control) can refer to the Verilog code design )