FPGA ‘for’ 循环

非常好的catapult学习书, catabult 可用于高级综合，由c产生vhdl/verilog(very nice book for catabult study)

在黑金AX7103板子上（A7）实现的demo工程中，存在一些bug。给与修正

NIOSII I2C接口模块及驱动程序，并含有测试程序。对想开发NIOS的工程师很有帮助(NIOSII I2C interface module and driver, and contains the test procedures. NIOS of engineers want to develop useful)

说明：  包含一个ALU，实现斐波那契数列的计算。1.接受两个6位二进制输入。2.通过手动输入的时钟驱动每个周期进行一次计算。3.结果输出到led灯（使用NEXYS4开发板）(Including an ALU to realize the calculation of Fibonacci sequence. 1. Accept two 6-bit binary inputs. 2. Each cycle is driven by a clock input manually. 3. Output to LED lamp (using NEXYS4 development board))

直接序列扩频通信（主要包括BPSK调制和BPSK解调以及PN码的产生）(Direct sequence spread spectrum communication (including BPSK BPSK modulation and demodulation, and the PN code generation))

Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)

这个程序详细的介绍了PS串口的编写，以及键盘的消抖。并显示在数码管上。经仿真验证，程序能够很好的完成设计目的。

在FPGA开发平台上，通过按键控制一个弹球小游戏。输出VGA显示信号输送到显示器上显示(On the FPGA development platform button control of a pinball game. VGA output signal is supplied to the display displayed on the display)

说明：  设计11位巴克码序列峰值检测器，巴克码相关器原理：巴克码相关器能够检测巴克码序列峰值，并且能够在1bits错误情况下检测巴克码序列峰值。(A 11-bit Barker code sequence peak detector is designed. The principle of Barker code correlator is that the Barker code correlator can detect the peak value of Barker code sequence and detect the peak value of Barker code sequence in the case of 1 bits error.)

说明：  引入了Verilog HDL硬件描述语言介绍了信号处理与硬线逻辑设计的关系，以及有关的基本概念。(In this paper, Verilog HDL hardware description language is introduced to introduce the relationship between signal processing and hardware logic design, as well as the related basic concepts.)