高速度 URDHAVA 乘数

基于Verilog HDL出租车计费系统的研制(Based on Verilog HDL Taxi Accounting System)

block-LDPC 译码VHDL 源代码(block-LDPC decode VHDL source)

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出-Using VHDL realize CPLD (EPM240T100C5) output of the VGA screen

USB的vhdl代码，具有很强的指导意义，对FPGA进行usb控制很有帮助！-USB vhdl code, which is of great guiding significance. the FPGA control usb helpful!

说明：  在FPGA内利用verilog实现数字上变频(apply the verilog to implement the digital up frequency)

数字频率计 数字频率计-Digital frequency meter digital frequency meter

The aim of the ECG simulator is to produce the typical ECG waveforms of different leads and as many arrhythmias as possible. My ECG simulator is a matlab based simulator and is able to produce normal lead II ECG waveform.

quartus 17.1 安装包，我现在用的就是(Quartus 17.1 installation kit, what I am using now is)

Verilog_HDL源码 -Verilog_HDL source Verilog_HD L FOSS Verilog_HDL FO

基于FPGA设计的电子密码锁是一个小型的数字系统，与普通机械锁相比，具有许多独特的优点：保密性好，防盗性强，可以不用钥匙，记住密码即可开锁等。(FPGA-based design of the electronic code lock is a small digital system. It has many unique advantages：good privacy and security , it do not need the key but remember password to unlock, and so on while it compare to ordinary mechanical locks.)