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基于FPGA的17阶FIR滤波器VHDL代码及说明文档
基于FPGA的17阶FIR滤波器VHDL代码及说明文档-fpga fir
- 2023-03-06 09:25:04下载
- 积分:1
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verilog
关于USB开发的verilog开发程序,非常的全面,学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)
- 2013-12-26 18:29:35下载
- 积分:1
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自己编写的只读存储器ROM16*8的试试很好用的
自己编写的只读存储器ROM16*8的试试很好用的-ROM 16*8
- 2022-05-13 03:23:21下载
- 积分:1
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e1framerdeframer
E1成帧器和解帧器的FPGA实现源码,测试可用(E1 Framer deframer)
- 2012-12-07 12:10:06下载
- 积分:1
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adder
说明: 通过四个半加器的互联,来实现四位加法器的电路结构(Through the interconnection of four and a half adder to achieve the four adder circuit)
- 2011-02-20 15:17:15下载
- 积分:1
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CORDIC16
16次迭代的CORDIC算法,精度很高,可应用于计算反正切值(16 iterations of the CORDIC algorithm, high accuracy, can be applied to calculate arctangent)
- 2010-06-01 15:23:27下载
- 积分:1
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I2C_code
与IP核配套的I2C-Master Core,包含了目前主流FPGA芯片的I2C实现,代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。(I2C-Master Core)
- 2010-05-22 22:12:26下载
- 积分:1
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rs232
用Verilog语言实现了UART串行通信协议(Verilog language used to achieve a UART serial communication protocol)
- 2015-08-21 20:26:16下载
- 积分:1
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5-15
用verilog语言实现基于DDS技术的余弦信号发生器,其输出位宽为16比特(Verilog language cosine signal generator based on DDS technology, the output bit width is 16 bits)
- 2013-04-18 22:58:05下载
- 积分:1
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src
v6 1x 3.125G rapidio协议工程代码(xilinx v6 rapidio data transmission protocol Practical project application engineering code)
- 2018-03-20 23:28:49下载
- 积分:1