ALTERA关于CCD的一些verilog程序，都通过运行无误的。

自己编写的经过QuartusII验证的Verilog HDL程序，可以实现常见功能-After QuartusII their written procedures for verification of the Verilog HDL, can achieve common features

这个源代码可以把DE2的板子作为一个USB设备使用，以便用PC软件去控制DE2-the source code can Dictyophora the board as a USB device use, to use PC software to control DE2

基于quartus 的一些程序 都是verilog 还是比较有用的 -Based on some of the procedures Quartus Verilog are still quite useful

六十进制计数器，显示0到60.可以用数码管显示。(Six decimal counter 0-60 can use the digital display.)

串行流水线格式:使用COrdic 算法计算反正切:向量模式下求角度 16bit :数据全部补码格式 (Serial line format: Use COrdic algorithm arctangent: seeking angle vector mode 16bit: full complement data format)

verilog 驱动TLC5510代码，TLC5510是高速的AD，可达20MHz(verilog code driven TLC5510, TLC5510 is a high-speed AD, up to 20MHz)

说明：  快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流(Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking tradition is a REG types of minority sorting, the use of RAM, the disorder for the RAM address of the number of exchange, to sort purpose, only to learn the exchange of.)

OFDM完美出图，信噪比，16QAM星座图，加窗信号时域和频域波形图(Perfect figure, OFDM SNR, 16 qam constellation diagram, add window signal time domain and frequency domain waveform figure)

This programa execute calc of CRC by use a table.

XAPP224 VHDL Data Recovery design file