ML605板子上的灯

实现verilog16位乘法器，verilog新手(achieve 16-bit multiplier)

E1成帧器和解帧器的FPGA实现源码，测试可用(E1 Framer deframer)

VGA的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-VGA

ML605评估板上的流水灯，可以实现每隔0.16秒进行+1操作 #include #include #include #include #include int main() {   char a[] = "-100" ;   char b[] = "123" ;   int c ;   c = atoi( a ) + atoi( b ) ;   printf("c = %d ", c) ;   return 0;

useful VHDL document for programmer

音乐和的设计，硬件语言描叙，书上的源代码哦(Music and design, hardware language describes, the book s source code Oh)

quartus 的220model 与 altera mf的库 用于fpga的modelsim仿真过程中添加到工程里面(the libary of 220 model and altera mf when we simulate the fpga project by modelsim)

数字钟vhdl主要分为正常显示与报时功能(Digital clock vhdl)

说明：  通过按键输入学号，并循环显示： 电路功能描述：通过Ego1上的按键输入自己的学号（8位10进制数），并存储在32位的寄存器中；8位10进制数输入完成后，实现滚动显示效果。(Enter the student number by pressing the key, and display it in a cycle: Circuit function description: input one's own student number (8-digit decimal number) through the key on ego1, and store it in 32-bit register; after the completion of 8-digit decimal number input, the scrolling display effect is realized.)

数字跑表 该跑表具有启动、复位、暂停、暂停后继续计时等功能 能显示的秒计数时间精确到小数点后第二位，即能显示**.**s 按钮设置防抖-Digital stopwatch in the stopwatch with start, reset, suspend, suspended after the time and other functions can show the seconds counting time accurate to the second place after the decimal point, that can show**.** s Anti-Shake button settings