Marquee procedures described in VHDL, for beginners to practice

点亮led流水灯，通过调用锁相环，可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)

基于fpga的spi通信测试 可与stm32进行spi通信测试(SPI communication test based on FPGA can test SPI communication with stm32)

一个verilog语言开发编写的简单的ddr3模型(A simple model ddr3, written with verilog language)

1.设计一个具有24进制计时、显示、整点报时、时间设置和闹钟功能的数字钟，要求时钟的最小分辨率时间为1s。2.多功能数字钟系统功能的具体描述如下：     计时：正常工作状态下，每日按24小时计时制计时并显示，蜂鸣器逢整点报时。     校时： 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

用FPGA实现dct变换。verilog语言实现，在quartus9.0中验证，含整个工程(dct transform verilog language in quartus9.0 verify, with the entire project)

说明：  用Verilog编写ad_9866的相应程序，在FPGA上实现相应功能(The corresponding program of ad_9866 is written with Verilog, and the corresponding functions are realized on the FPGA.)

说明：  本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)

此功能是实现曼彻斯特编码的Verilog代码，经过在xilinx sp6上实际运行证实可行。(This function is to achieve the Manchester code Verilog code, through the Xilinx SP6 actual operation proved.)

本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)

Verilog版的C51核(OC8051)-Verilog version of the C51 core (OC8051)