西北逻辑 （Altera） 特别提款权 SDRAM 控制器

数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法(Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis and computer simulation of specific methods)

CYPRESS官方给的FPGA程序，用于调试USB3.0接口(Verilog source files for debugging USB3.0 interface)

用verilog编写的分辨率提高的源代码 采用双线性插值(Written resolution with the verilog source code to improve the use of bilinear interpolation)

C++获取CPU占用率，一个类和一个头文件(Gets the CPU Use rate)

说明：  altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。(altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.)

半带滤波器，工作在采样率122.88Msps上(Half-band filter, working at the sampling rate of 122.88 Msps)

4*4键盘小程序 两种算法内附检查LED(4* 4 keyboard applet containing two algorithms check the LED)

vs自定义插件开发,带卸载功能,经测试完全可用，分享给大家，可以学习！(vs custom plug-in development, with the uninstall feature, has been tested and is fully available for everyone to share, you can learn!)

该程序用来实现电话计时以算取费用，比较简单(telephone cost metering verilog code)