-
dpll
数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法(Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis and computer simulation of specific methods)
- 2017-04-04 23:13:28下载
- 积分:1
-
AN65974
CYPRESS官方给的FPGA程序,用于调试USB3.0接口(Verilog source files for debugging USB3.0 interface)
- 2020-11-30 17:49:27下载
- 积分:1
-
resolutionquartusII
用verilog编写的分辨率提高的源代码 采用双线性插值(Written resolution with the verilog source code to improve the use of bilinear interpolation)
- 2021-05-14 18:30:02下载
- 积分:1
-
CPU
C++获取CPU占用率,一个类和一个头文件(Gets the CPU Use rate)
- 2015-01-23 11:15:32下载
- 积分:1
-
testbench
说明: altera 最新的CYCLONE IV的pci-e核的testbench,VHDL源程序。(altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.)
- 2010-04-22 10:20:24下载
- 积分:1
-
03_hbf_test_128m22
半带滤波器,工作在采样率122.88Msps上(Half-band filter, working at the sampling rate of 122.88 Msps)
- 2020-12-23 10:59:07下载
- 积分:1
-
4x4-key
4*4键盘小程序 两种算法内附检查LED(4* 4 keyboard applet containing two algorithms check the LED)
- 2013-07-28 22:19:49下载
- 积分:1
-
RecentProjectCleaner
vs自定义插件开发,带卸载功能,经测试完全可用,分享给大家,可以学习!(vs custom plug-in development, with the uninstall feature, has been tested and is fully available for everyone to share, you can learn!)
- 2014-12-24 11:35:54下载
- 积分:1
-
telephone-cost-metering
该程序用来实现电话计时以算取费用,比较简单(telephone cost metering verilog code)
- 2013-11-03 19:45:00下载
- 积分:1
-
ADV7513 HDMI条形显示,支持1920*1080,最高收入时钟165MHz,完整的Verilog语言实现,并且有完整的IIC驱动代码
- 2022-02-24 11:32:13下载
- 积分:1