Sopc technology

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)

verilog编写，巧妙的通过计数方式完成了三角波的波形，可直接对da输出。(verilog written, cleverly accomplished by counting the triangular waveform can be output directly to da.)

altera官方的各种有用的参考资料，都是自己收集的，遇到问题可以很方便的查看(altera official variety of useful references, are their own collection, problems can easily view)

基于FPGA的16QAM调制程序,基于verilog开发环境(16QAM modulation program based on FPGA-based development environment verilog)

微分器：利用数字锁相环进行位同步信号提取的关键模块(Differentiator: the use of digital phase-locked loop for bit synchronous signal extraction of key modules)

8bit/10bit编码Verilog实现(8bit/10bit Verilog Code)

说明：  用zynq实现片内的数模转换，基于最新的zynq平台(zynq xadc on FPGA arm)

W elcome to X CELL, the new Xilinx customer newsletter. By sending us your development system registration card you automatically became n charter subscriber to this quarterly publication. It is our intent to make this an informative, easy to read, responsive and-hopefully- interactive newsletter. We want to supply you with early and correct information, tell you about the status of our products and about our plans, about bugs and their workarounds, give you applications ideas and convey to you some of the en thusiasm that we feel for our Programmable Gate Arrays. If you have questions or suggestions, please send them to me. II Letters to the Editor make a newsletter more lively. Peter Alfke, Editor

使用DDR3IP核进行仿真，写入读取数据(Using DDR3IP core to simulate, write and read data)