PLD与8051接口的参考设计 Xilinx提供的verilog源代码

说明：  ad9649的fpga驱动程序,FMC接口，基于Xilinx KC705(AD9649 Evaluation Board, FMC Interposer & Xilinx KC705 Reference Design)

UART模块的VHDL语言设计(Design of VHDL language based on UART module)

适用于FPGA的SOPC方面的元器件添加，如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT

本实验主要是在FPGA上实现FIR数字滤波器的功能，不仅有工程文件，还具有论文资料。(This experiment mainly realizes the function of FIR digital filter on FPGA, not only has the engineering document, but also has the thesis information.)

NIOS II IDE 编程， FLASH测试程序，仅供参考。-NIOS II programming IDE, FLASH testing procedures, for information purposes only.

文档主要是关于TFT-LCD的相关资料，是有关TFT-lcd芯片的结构与设计理念，对于在这方面学习的朋友有比较大帮助(402 output thinfilm transistorliqu idcrystal display(TFT-LCDdriver integrated circui(ICwith power controlbasedon the number of color stobe displaye disdescribed. Toachievethistypeofpowercontrol,referencevoltagebuffersare turnedonandoffaccordingtotheselectednumberofcolors.)

Verilog语言编写的电话计费系统，这只是源代码，需要在quartusII等软件下运用-Verilog language telephone billing system, this is only the source code, the need to use software such as quartusII

VHDL数字系统设计和工程实践1，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, one that contains principles, truth table and schematic, as well as VHDL source code.

说明：  FIFO: First in, First out 代表先进的数据先出，后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO，根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)

二维DCT，FPGA实现JPEG压缩中的二维DCT(dct)