PLD与8051接口的参考设计 Xilinx提供的verilog源代码

调整iq幅度不平衡的模块，可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)

说明：  采用FPGA（现场可编程门序列）编写VHDL语言设计多路同步脉冲发生器，对信号进行分频处理，实现四路信号相位相差T/16和T/8的延迟相位输出，实现的四路脉冲与传统的脉冲同步器不同，它具有高集成度，高通用性，容易调整和高可靠性等特点。(Using FPGA (field programmable gate sequence) to write VHDL language to design multi-channel synchronous pulse generator, to divide the frequency of the signal, to achieve the four-way signal phase difference T / 16 and T / 8 delay phase output, the realization of the four-way pulse is different from the traditional pulse synchronizer, it has the characteristics of high integration, high-throughput, easy adjustment and high reliability.)

通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。(Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.)

SDRAM驱动器，自己项目利用的，已经经过实际验证(sdram controller)

可以直接下载到芯片用的带有FIFO的完全UART程序，vhdl语言编写。-Can be directly downloaded to the chip used in the complete UART with FIFO procedures, vhdl language.

如何用VHDL语言对时钟进行分频以达到计数目的(how to achive counting by VHDL Language)

双端口静态RAM的VHDL程序，具体芯片型号为IDT7005(DUAL-PORT STATIC RAM)

Altera的CycloneIII Start Board,使用的PFGA是3C25，包括原理图和PCB，用Cadence Allegro打开-Altera

用于altera公司DE2开发板上SD_Card_Audio的实例-DE2 development company for the altera board SD_Card_Audio examples

说明：  基于FPGA，用verilog hdl语言实现串口收发实验(Based on FPGA, using Verilog HDL language to achieve serial port transceiver experiment)