PLD与8051接口的参考设计 Xilinx提供的verilog源代码

基于VHDL语言的3级序列的产生，可以循环产生周期为7的m序列 -Based on the VHDL language for selecting the three sequences, you can have a cycle for cycle 7 m sequence

cordic的verilog程序 用ＦＰＧＡ实现-CORDIC FPGA using the Verilog procedures realize

This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.

fpga下的七段数码管显示 大 学 实 验 报 告-fpga under the seven-segment digital tube experiment reports that the University

说明：  基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)

T他的这项工作的目的是调查闩锁，拖鞋，并注册。

802.11a Transmitter implementation Using Verilog

VHDL与源代码包-and VHDL source code

设计制作一个检测4*4矩阵键盘的按键编码的实验，把实际按键的键值的八位编码先转换成从0000—1111的编码，再译成数码管能识别的八位编码，在数码管动态显示时，4*4矩阵键盘的第一行对应00—03，第二行对应04—07，第三行08—11，第四行对应12—15。(Design a 4* 4 matrix keyboard key coding experiments to detect the key the actual key octet coded first convert from 0000-1111 encoding, and then translated into digital tube to identify the eight coding, digital tube dynamic display, the first line of the 4* 4 matrix keyboard corresponding to 00-03, the second line corresponds to 04-07, the third line of 08-11, the fourth line corresponds to 12-15.)

利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter