本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块...

说明：  本例的源描述超过了演示版限制的300行, 如果您需要对其进行编译与模拟,请与北京理工大学 ASIC研究所联系,获取Talent系统的完全版本. 联系方法: 电话:010-68912434 (The source described in this case than the demo version of the 300 line limit, if you need to be compiled with the simulation, please contact ASIC Institute of Beijing Institute of Technology to obtain the complete version of Talent system. Contact: Tel :010-68912434)

8051MCU在FPGA上实现的源代码，用VHDL语言编写-8051MCU in the FPGA to achieve the source code, using VHDL language

this is the source code we have been working on for our project using altera de2 board. the code can be run but some of it miss the end game module, while some doesn t have the complete vga code

单片机通过总线，将占空比和频率送到CPLD/FPGA中，并控制PWM输出.采用Verilog HDL语言编写。(Microcontroller by bus, the duty cycle and frequency sent to the CPLD/FPGA in, and control the PWM output. Using Verilog HDL language.)

通过用vivado完成一个流水灯项目手把手教你如何使用vivado，内容十分详细。(Using vivado to complete a running light project, you can learn how to use vivado by hand. The content is very detailed.)

verilog支持noise噪声的端口port, 可以用于仿真运行. 评估噪声影响 Verilog port that supports noise and can be used for simulation run. Evaluate noise effects

黑金动力原创nios ii教程，介绍了硬件、软件开发流程，提供了led、中断、串口、rtc、spi、iic、定时器等十多个实验的详细介绍(Alinx original nios ii tutorial, this paper introduces the hardware and software development process, and provides led, interrupt, a serial port, the RTC, spi, iic, timer and so on more than a dozen experiments in detail)

说明：  实现了QPSK的调制，使用了ise自带的dds的IP核(QPSK is modulated and the IP core of DDS is used in ise.)

Priority encoder in VHDL.

本程序是在Quartus7.2环境下编译的一个简单的(2,1,3)卷积码，能够成功地编译和仿真。(This procedure is in circumstances Quartus7.2 compile a simple (2,1,3) convolutional code, can successfully compile and simulation.)