VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验...

de2_clock on altera de2 board

SOC经典教程，包含案例以及完整的代码等等。(SOC classic tutorial, including cases and complete code, and so on.)

基于QuartusII环境下以模块化的形式做成的视频复合同步信号。(QuartusII-based environment to create the form of modular composite video sync signal.)

一个简易的频率计，主要用检测在一定范围内的频率，当然频率过大会有误差(A simple frequency meter, mainly used for testing in a range of frequencies, of course, frequency of errors over the General Assembly)

设计一个简单的FIR滤波器，并按要求确定滤波器的系统函数。(Design a simple FIR filter, and determine the filter according to the requirement of system function.)

该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)

说明：  基于altera fpga的fir IP核实现希尔伯特变换，有matlab仿真(Based on Altera FPGA fir IP core to achieve Hilbert transform, matlab simulation)

用VHDL开发的棒球游戏，可以在QuartusII环境下编译，适用于各种FPGA开发板。-VHDL development of the baseball game, in QuartusII environment compiler, apply to all FPGA development board.

altera remote updata cyclone5 平台例程，无nios核版本(altera remote updata cyclone5 platform routine do not use nios)

说明：  THU微纳电子系ic设计课程大作业，使用verilog实现CNN加速器，含一层卷积和池化，仿真通过。(a CNN accelerator written in VerilogHDL, including one conv layer and one pooling layer, simulation passed)