VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验...

VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design

建立了单相的PWM整流器电路闭环控制的仿真模型。版本R2007(The simulation model of the closed-loop control of single-phase PWM rectifier circuit. Version R2007)

4tap FIR filter in verilog code

256字节深度的RS232串口程序,共分4个模块,顶层文件FIFO程序串口收和串口发.经过测试已用于产品.可靠!-Depth of 256-byte Serial RS232 procedures, divided into four modules, top-level document procedures FIFO serial and serial-fat collection. After the test has been used in products. Reliable!

Matlab - to hdl code for square root

有很多例子及测试代码，对初学者很有帮助，很容易上手-a lot of examples and test code, useful for beginners, it is easy to get started

本源码为Nios II的开发示例,主要演示Nios II的I2C总线设计。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II I2C-bus design. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

这是led流水灯的vhdl描述，很好的啊-led s hdl describe

本文以 VHDL 语言编码得到了 AMBA 与 AHB 总线仲裁。这里在本文中，我们设计了 AMBA 总线协议，将用于多奴隶通信环境，多主

利用FPGA内核产生SPWM波，并且频率可调(The FPGA kernel is used to generate SPWM waves, and the frequency is adjustable)