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Toplevel VHDL Structural model of a system containing 8051
Toplevel VHDL Structural model of a system containing 8051
-Toplevel VHDL Structural model of a system containing 8051
- 2022-11-19 06:20:03下载
- 积分:1
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24_Timer
说明: 使用Verilog编写的24位定时器,具有apb 总线接口,可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
- 2021-04-27 21:38:44下载
- 积分:1
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clock_6
ds1302时钟驱动程序,已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)
- 2020-06-24 12:00:02下载
- 积分:1
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clock_6
说明: ds1302时钟驱动程序,已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)
- 2020-06-24 12:00:02下载
- 积分:1
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lab4
lab report for lab 4
- 2019-04-17 21:17:08下载
- 积分:1
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fir
该程序实现了一个FIR滤波加速器,该程序在FPGA板上开发,通过使用VHDL语言来定义RS232端口的使用(design a FIR Filter Accelerator based on FPGA board and RS232 interface using VHDL language. )
- 2013-06-07 06:27:32下载
- 积分:1
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FIFO
FIFO的源代码,对FIFO设计有帮助,有借鉴意义,帮助学习VHDL编程(FIFO of the source code, on the FIFO design help, there is reference to help learn VHDL programming)
- 2008-04-29 09:00:11下载
- 积分:1
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比较实用的ps2键盘源码 可以在SOPC中进行添加组件 以实现自己所需的功能...
比较实用的ps2键盘源码 可以在SOPC中进行添加组件 以实现自己所需的功能-Comparison of practical ps2 keyboard source code can be carried out in the SOPC components add to the functionality required to realize their own
- 2023-01-08 03:55:02下载
- 积分:1
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add(FLP)
一个32位元的浮点数加法器,可将两IEEE 754格式内的值进行相加(A 32-bit floating-point adder can be both within the IEEE 754 format to add value)
- 2021-04-06 18:19:02下载
- 积分:1
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全部通过,是我的精心设计,完全满足初学者的要求。
全部通过,是我的精心设计,完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
- 2022-03-02 01:44:58下载
- 积分:1