8位7段LED显示源码，扫描显示，稳定高效

使用verilog语言，滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)

说明：  使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

modelsim教程仅供学习-modelsim tutorial to learn only

脉冲多普勒雷达回波信号相干积累的VHDL源程序-pulse Doppler radar echo signal coherent accumulation of VHDL source

直接数字式频率合成器DDS设计、Verilog。 产生的信号可以是正弦波或方波、三角波、锯齿波等，自选。 采用DDS技术，将所需生成的波形写入ROM中，按照相位累加原理合成任意波形。 此方案得到的波形稳定，精度高，产生波形频率范围大，容易产生高频。 本实验在设计的模块中，包含以下功能： （1）通过 freq 信号输入需要的频率的值； （2）通过 wave_sel 信号选择所需的波形； （3）通过 amp_adj 信号选择波形放大的倍数。(DDS design of direct digital frequency synthesizer, Verilog. The generated signal can be sinusoidal or square wave, triangular wave, sawtooth wave and so on, optional. By using DDS technology, the required waveforms are written into ROM, and arbitrary waveforms are synthesized according to the principle of phase accumulation. The waveform obtained by this scheme is stable, accurate and easy to generate high frequency waveform. This experiment includes the following functions in the designed module: (1) Input the required frequency value through freq signal; (2) Choosing the required waveform by wave_sel signal; (3) Select the multiplier of waveform amplification by amp_adj signal.)

通过EMIF连接fpga与dsp的代码-Through the EMIF connection FPGA code with dsp

说明：  实现基于黑金开发板的实时时钟功能，显示时分秒(Realize the real-time clock function based on black gold development board, display time, minute and second)

说明：  this files describes how to build i2c block modules in verilog hdl and programming them on an fpga device

基于FPGA的 温度传感器 DS18B20接口设计-FPGA DS18B20

原理图输入法制作的32位加法器。。。。。。。。(adder32)