ov5640驱动代码

基于FPGA设计的电子密码锁是一个小型的数字系统，与普通机械锁相比，具有许多独特的优点：保密性好，防盗性强，可以不用钥匙，记住密码即可开锁等。(FPGA-based design of the electronic code lock is a small digital system. It has many unique advantages：good privacy and security , it do not need the key but remember password to unlock, and so on while it compare to ordinary mechanical locks.)

8位并行转穿行发送程序，波特率可自行设置，经检验有实用效果(8-bit parallel transfer walk through the sending program, the baud rate can be set up their own practical effect inspection)

AHB 主设备和从设备在 verilog 实施。在项目中定义的主要功能是： 所有类型的爆裂增量、 缠绕、 连续和非序贯、 流水线的交易。试验台进行了核查

The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last

通过MATLAB产生单脉冲信号的数据，存储下来作为verilog代码实现的DDS的数据源，用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)

代码由Verilog语言编写，可以实现HDLC协议，主要由发送模块、接收模块和cpu接口三个大模块组成，可以替代集成芯片PT7A6525。

基于FPGA 黑金ALINX 515的 ADDA采样模块源码（需调试）(ADDA Sampling Module Source Code Based on FPGA Heijin ALINX 515)

利用硬件（可编程逻辑器件FPGA）实现密码算法SHA256，在FPGA中嵌入软核NIOSii，在NIOSii上进行软件编程。硬件EDA工具为ALTERA的Quartus ii，软件IDE为eclipse（嵌在Quartua中）。

pll(phase locked loop) is used to fix the circuit to particular frequency

yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)