内嵌BRAM设计LIFO堆栈

用于压缩感知 OMP 算法非常适合于压缩感知

说明：  多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)

这是altera公司的DE2-35开发板下的一个液晶显示屏源程序代码工程，液晶显示屏是友晶公司的，包括液晶显示屏的驱动以及显示等模块有需要的人，可以下载 (Altera DE2-35 development board of the company, a liquid crystal display source code engineering, LCD display the Terasic, including LCD driver module and display needs, you can download)

CH2 VHDL 数字电路参考书所有程序2-CH2 VHDL digital circuit two reference books all procedures

Multiplexer styles in VHDL

可以产生ASK FSK PSK 等调制信号。非常好用已经实现了所有功能。在硬件测试通过了(Can generate ASK FSK PSK modulated signals and so on. Is very easy to use all the features has been achieved. On the hardware test of the)

这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章，实用性很强的，在这里也感谢这篇文章的作着-This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was

基于verilog语言的数据选择器，包括数据选择器的测试模块 (verilog language based on the data selector, including data selection for the test module)

说明：  displayport 参考设计，可以对比自己工程做验证，另有参考设计XAPP1178未找到，采用方案为DP159 + Artix7 FPGA(xilinx displayport sink design)

基于VHDL+FPGA的神经网络设计，实现简单的字符识别(Design of Neural Network Based on VHDL+FPGA to Realize Simple Character Recognition)