内嵌BRAM设计LIFO堆栈

若农场路无车辆，则在高速路保持绿灯。在探测农场路有车辆，高速路上的交通灯应由绿到黄，再到红，并允许农场路方向灯变绿，绿灯亮一段时间，由绿变黄再到红。(If there is no vehicle on the farm road, keep the green light on the highway. There are vehicles on the farm road, the traffic lights on the high speed road should be green to yellow, and then red, and allow the farm road lights to turn green, the green light for a period of time, from green to yellow, then to red.)

数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms

xilinx 开发板程序，VGA控制显示-Xilinx development board procedures, VGA display control

A complete VHDL source code to 5-storey elevator

altera公司cpld/fpga开发软件quartus2中文使用教程-altera company cpld/fpga development of software to use Chinese quartus2 Guide

这是FPGA的一个简单例程，LED键盘显示程序，非常时候大家入门学习-This is the FPGA, a simple routine, LED keyboard display program, very time we started to learn

我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application

本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。-this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.

这是使用VHDL编写的交通灯程序,供大家交流学习-This is the use of VHDL prepared by the traffic lights procedures for the exchange of learning

Verilog HDL数字系统设计项目，频率可调的任意波形发生器，可以输出正弦波、方波、三角波和反三角四种波形(Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform)