内嵌BRAM设计LIFO堆栈

实光电码盘的输出数据的四倍频，使码盘输出精度提高四倍。-real photoelectric encoder output data of the four frequency, accuracy encoder output increased by four times.

BCH3.c,提供m<21以下的所有码长的BCH编解码模块。以供大家参考。谢谢(BCH encoder&decoder GF(2^m) m<21)

Frequency meter Verilog implementation for Xilinx XC2C256. MT10T7 7-seg LCD used for output.

高速FIFO，verilog设计。速度高达130Mhz(High-speed FIFO, verilog design. Speed up to 130MHz)

该实验完成的功能是STM32与FPGA通信(The function of the experiment is STM32 and FPGA communication)

计数器的程序，eda编程用的，vhdl语言编程，大家下载看看吧(Program counter, eda programming used, vhdl programming )

UART communication on SPARTAN 6 it contains tx and rx

OFDM系统中的相位跟踪模块（Phase_Tracking）的FPGA实现-Phase_Tracking in OFDM sysytems

basic cpu design in verilog

数字下变频（DDC）在如今基于软件无线电的架构中对系统的整体性能决定性的影响，代码为基于Matlab的4通道DDC程序，程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值(Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value)