内嵌BRAM设计LIFO堆栈

SMT32F4 i2s 全双工配置，自己测试OK的，大家可以看看(SMT32F4 i2s 全双工配置)

RS 编码和解码Verilog Code, 实现了RS（544,514)的编码和译码；(-RS Coding and Decoding Verilog code，　implement RS（544,514))

design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an analogue an analogue input using SPI MCP3202 12-Bit A/D converter to generate the digital data stream and then the digital data will be used to generate an analogue output using Analog Devices 8-bit SPI AD7303 D/A converter.

SRAM简单测试，测试其性能及其速度，判断SRAM是否可用(Test its performance and speed to determine if SRAM is available)

rda1846 + pic18f2552 usb circuit schematic.

Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written

FPGA的SRAM存储器的控制程序，包括时序测试-FPGA

说明：  how to come ture a costas loop in FPGA with verilog,it is very useful on project

实现任意倍数的倍频,帮助大家解决VHDL倍频问题,(The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,)

说明：  matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)