内嵌BRAM设计LIFO堆栈

基于FPGA的ip核FIR低通滤波器，实现滤波功能，简单好用(FPGA-based ip core FIR filter for filtering function, easy to use)

例程是基于quartus的，FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)

基于fpga的电子血压计。pdf文档，好用，内容清楚简单，转载而来(Electronic sphygmomanometer based on fpga)

基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2

VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)

这是一本关于VHDL编程的书籍,网上突然发现的,相信对相关人员会有所用途.-This is a book on VHDL programming, on-line suddenly found, I believe that the relevant staff will be use.

从零开始的Xilinx DDR3 控制程序编写教程，利用MIS IP核通过自编逻辑实现对DDR3的读写，强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)

说明：  可以获取各种字符，并在数码管显示出来，非常的靠谱且稳定(Various characters can be acquired and displayed on the digital tube.)

SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)

这段代码是用VHDL解释椭圆曲线密码术的。这段代码包含了使用FPGA板进行ECC加密的必要算法！ ；