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通过VHDL语言的例子,FPGA原型的VHDL例子(chapter3-part1)
应用背景关键技术本书采用“做中学”介绍VHDL和FPGA技术的概念和设计人员通过一系列的实验方法。
- 2023-04-20 18:05:04下载
- 积分:1
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dianziqin
运用quartus 软件模拟的电子琴,实现按键出现不同音调的音乐。(Quartus software simulation using keyboard, keys appear to achieve different tones of music.)
- 2013-07-03 14:57:05下载
- 积分:1
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example
一个电子秒表,最大显示59.99,具有暂停和reset功能(An electronic stopwatch, the maximum display 59.99, with a pause and reset functions)
- 2013-12-17 12:28:14下载
- 积分:1
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基于EDA技术设计4位十进制数字频率计的系统方案
基于EDA技术设计4位十进制数字频率计的系统方案-Based on EDA technology design four decimal system solutions Cymometer
- 2022-03-21 02:07:27下载
- 积分:1
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IIC and xlinx official description of spi interface
xlinx官方的iic和spi接口的描述-IIC and xlinx official description of spi interface
- 2022-03-26 12:21:51下载
- 积分:1
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library
Library OLED SSD1305
- 2012-11-01 21:21:26下载
- 积分:1
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DW8051_ALL
包中包括,
DW8051完整的Verilog HDL代码
两本手册:
DesignWare Library DW8051 MacroCell, Datasheet
DesignWare DW8051 MacroCell Databook
三篇51论文:
基于IP 核的PSTN 短消息终端SoC 软硬件协同设计
Embedded TCP/ IP Chip Based on DW8051 Core
以8051为核的SOC中的万年历的设计 (DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!)
- 2021-05-07 09:28:36下载
- 积分:1
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CRC-Verilog
此是进行循环冗余效验的Verilog编码,适合多种标准,如CRC16(this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY)
- 2007-01-03 10:47:43下载
- 积分:1
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tcoug
Synopsys®
Timing Constraints and Optimization
User Guide
- 2014-08-23 17:37:56下载
- 积分:1
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ArhivaAdrian
Anticipated Adder for Xilinx
- 2011-11-15 06:57:02下载
- 积分:1