FPGA的SRAM存储器的控制程序，包括时序测试

应用背景关键技术本书采用“做中学”介绍VHDL和FPGA技术的概念和设计人员通过一系列的实验方法。

运用quartus 软件模拟的电子琴，实现按键出现不同音调的音乐。(Quartus software simulation using keyboard, keys appear to achieve different tones of music.)

一个电子秒表，最大显示59.99,具有暂停和reset功能(An electronic stopwatch, the maximum display 59.99, with a pause and reset functions)

基于EDA技术设计4位十进制数字频率计的系统方案-Based on EDA technology design four decimal system solutions Cymometer

xlinx官方的iic和spi接口的描述-IIC and xlinx official description of spi interface

Library OLED SSD1305

包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 (DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!)

此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16(this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY)

Synopsys® Timing Constraints and Optimization User Guide

Anticipated Adder for Xilinx