verilog触发器

基于vhdl语言的15位gold序列的设计的开端一部分程序(Vhdl language based on sequences of the 15 gold as part of the beginning of the design process)

用zynq实现片内的数模转换，基于最新的zynq平台(zynq xadc on FPGA arm)

FPGA与DAC芯片的SPI接口驱动，实现串行数据的传输。(Realizing the communication between FPGA and DA chip)

本程序实现数字钟系统，有整点报时功能，可显示切换年月日，定时功能(Digital clock system of this program, with the whole point timekeeping function, can display the date, the timing function)

thesis for simple virus detection processor which is developed in xilinx

51单片机测试程序，ＩＣ:UC1676,4线串口(51 MCU test program, IC:UC1676 4-LINE, SPI INTERFACE)

Verilog HDL 写的SVPWM 算法的实现，使用的是altera 风暴系列的FPGA，占用资源1w+逻辑宏单元(Verilog HDL ，SVPWM)

这是用altera的DE2-115做的，藉由各種播放軟體 这是用altera的DE2-115做的，藉由各種播放軟體 这是用altera的DE2-115做的，藉由各種播放軟體 这是用altera的DE2-115做的，藉由各種播放軟體

这是rs（255，223）编码的verilog源程序。里面有：encode、decode、test－bench等文件。(This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.)

文档包括双线性插值算法和最近邻域算法的详细介绍，以及算法的相关计算。(Documentation includes bilinear interpolation algorithm and the nearest neighbor algorithm which is described in detail, as well as algorithms related calculations.)