通过VHDL语言进行数字信号处理的FIR操作，可以很好的实现滤波功能，有很好的作用，...

EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)

PS2键盘实验Verilog HDL代码(PS2 keyboard experiment Verilog HDL code)

王金明：《Verilog HDL 程序设计教程》程序-Wang Jinming:

FPGA实现串口发送 Verilog 语言(Serial reception FPGA Verilog language.)

在Quartus环境中，采用VHDL语言编写的出租车计费系统，系统共分为分频、状态切换、记程、计费等模块，模仿现实中出租车计费。-In the Quartus environment, the use of VHDL language taxi billing system, the system is divided into sub-frequency, state switching, recording process, billing and other modules, to imitate reality, taxi billing.

一个PS2 IP CORE(VHDL) for FPGA-A PS2 IP CORE (VHDL) for FPGA

当时是用于课程设计而编写的代码，经过的运行没有错误。精确率很高。基于FPGA的数字频率计VHDL源码（精确到1.1hz至20.0mhz）

code for fft non synthesisable in xilinx ise

Verilog 写的HDMI接口源程序及说明文档(HDMI interface verilog code and specificaiton paper)

cpld与单片机接口设计,利于电子设计及应用- Interface design between microprocessor and cpld ,suit for IC design and application