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gps
基于fpga和dsp架构的gps接收机的设计和实现(Design and Implementation of gps Receiver Based on fpga)
- 2017-05-25 17:44:51下载
- 积分:1
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subway-ticket-vending-system
本设计是基于FPGA设计一个地铁自动售票系统。 本设计采用自顶向下的模块化设计方法,基于FPGA使用VHDL语言设计制作一个地铁自动售票控制系统,该系统能出售2条线路3种不同价位的票,完成售票、找零、显示等功能。(The design is based FPGA design of a subway ticket vending system. This design uses a top-down, modular design method, a subway ticket vending control system based on FPGA using VHDL language design, the system can sell two lines of different priced tickets, complete the ticket, give change, display and other functions .)
- 2013-02-27 12:59:49下载
- 积分:1
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I2C is a two
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of
data exchange between devices.
- 2022-10-23 17:25:02下载
- 积分:1
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和picoblaze完全兼容的mcu ip core
和picoblaze完全兼容的mcu ip core-And PicoBlaze fully compatible mcu ip core
- 2023-08-22 23:25:04下载
- 积分:1
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verilog实现的“BCD/七段译码器”。
verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."
- 2022-12-23 05:15:02下载
- 积分:1
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qam_64
64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核(64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS)
- 2021-03-02 23:29:33下载
- 积分:1
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dds
DDS实验 matlab 与quartus 的完美结合(DDS experimental combination of matlab and quartus)
- 2010-05-08 08:51:48下载
- 积分:1
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实现BCD码的加法,用VHDL实现,是书籍上配套的
实现BCD码的加法,用VHDL实现,是书籍上配套的-BCD ADDER,Using VHDL
- 2022-02-10 02:09:10下载
- 积分:1
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Verilog 经典实例,完整源码与大家分享
Verilog 经典实例,完整源码与大家分享-Verilog classic example of a complete source to share with you
- 2022-07-03 12:56:56下载
- 积分:1
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VHDL硬件描述语言作业
VHDL硬件描述语言作业-VHDL hardware description language operations
- 2022-03-19 16:26:25下载
- 积分:1