通过VHDL语言进行数字信号处理的FIR操作，可以很好的实现滤波功能，有很好的作用，...

吠陀复用代码执行乘法的4位和8位使用进位选择加法器

设计的结构是纹波进位加法器，但执行的操作是加法和减法，两种操作都是32位的，具体取决于控制信号。如果控制信号为“1”，则选择减法，然后选择“0”，然后选择加法

偶数分频，包括验证程序，verilog实现，可综合-Even-numbered sub-frequency, including the verification process, verilog realize, can be integrated

说明：  实现简单的硬件加法器、除法器，实现源码文中注释(Realize simple hardware adder and divider, realize source code)

基于FPGA的17阶FIR滤波器VHDL代码及说明文档-fpga fir

自己用verilog编写的crc16-ccitt码的产生，是并行的。(Crc16-ccitt code written in verilog generate parallel.)

CY7C63723 功能及其引脚描述，外围电路和仿真数据(The CY7C637 is an 8-bit RISC OTP microcontroller.)

vhdl语言主要描述语句的说明和使用方法，内附例子可供学习提高-VHDL language description of the main description of statements and the use of methods, containing examples for learning improve

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )

多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)