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LIP6903CORE_CSC_RGB2YUV
CSC RGB2YUV Verilog source code
- 2011-02-28 20:06:13下载
- 积分:1
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DDS_DAC_Output
本工程使用A7系列FPGA产生DDS,用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)
- 2019-05-06 10:05:10下载
- 积分:1
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IIC controller for Sopc Builder
IIC控制器 for Sopc Builder-IIC controller for Sopc Builder
- 2022-05-21 02:21:43下载
- 积分:1
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AD_sample
AD采集模块,设计模块采集AD5270的输出数据(AD Collection module
Design module to collect the output data of AD5270
)
- 2020-11-18 16:19:39下载
- 积分:1
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rs_encoder
适应多个模式的rs编码,Verilog,选择对应的多项式(RS coding adapted to multiple modes.)
- 2020-06-16 04:40:02下载
- 积分:1
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COSTAS_LOOP
用verilog编写的科斯塔斯环,希望有帮助(Costas loop written in verilog helpful)
- 2012-10-31 23:01:23下载
- 积分:1
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FPGA_PSK
说明: 可以实现2PSK的信号调制,已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)
- 2019-05-09 16:29:17下载
- 积分:1
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cordic
CORDIC(Coordinate Rotation Digital Computer)算法即坐标旋转数字计算方法。 CORDIC算法,能够通过平移和累加快速实现基础的数学函数,包括三角函数,开方,指数,对数,平方根等函数。(CORDIC (Coordinate Rotation Digital Computer) algorithm for the coordinate rotation digital calculation. CORDIC algorithm can be achieved through the rapid translation and accumulation based on mathematical functions, including trigonometric, square root, exponential, logarithmic, square root and other functions.)
- 2020-06-29 13:40:02下载
- 积分:1
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AHB_to_Wishbone_Verilog
说明: 该源代码包是AHB总线到Wishbone总线的交接器,包括以下4个部分:RTL源代码,测试平台,软件测试程序,说明文档。(This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.)
- 2021-01-22 14:48:40下载
- 积分:1
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100powertips
these are the source codes for the book " 100 power tips for FPGA designers"
- 2012-08-20 14:59:29下载
- 积分:1