RS编解码的FPGA实现

常用的异步FIFO empty full 标志位 读出剩余usedrd 写入数量usedwr

Verilog经典教程，非常好的资料！值得一看！(Classic Verilog tutorials, very good information! Worth a visit!)

使用verliog设计实现LUT查找表乘法器，通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)

e200 riscv open code user guide

VHDL TESTBENCH书写规范，对学习FPGA的同学很有帮助，掌握仿真语言书写规范。(VHDL TESTBENCH description of the norms, the students learn FPGA helpful, master the language of simulation techniques)

针对电力电子领域的需求，采用自然采样法设计了一个全数字三相SPWM信号产生系统IP软核．通过数字频率合成技术实现了对电源频率的辅确控制．使电源频率精度达到16位．其中。通过调节控制参数．分别实现了电源频率与载波频率的7级、8级控制．最后。搭建了基于FPGA的测试系统．验证了系统功能的正确性．(According to the requirement of power electronics, the natural sampling method for the design of a full digital three-phase SPWM signal generation system. The power frequency of IP core is the auxiliary control is implemented through digital frequency synthesis technology. The power frequency accuracy of 16. By adjusting the control parameters, 7 and 8 levels of power frequency and carrier frequency are realized respectively. Finally, the control of the power frequency and carrier frequency is realized. A test system based on FPGA is built, which verifies the correctness of the system function)

高频卡读写原理及技术编程应用--卡的读取，写入。(High-frequency card reader technology)

基于FPGA的GFP（通用成帧协议）封装数据成帧的实现。(FPGA-based GFP (Generic Framing Protocol) encapsulated data Framing realized.)

2ask调制与解调的源代码，经过测试可用(2ask modulation and demodulation source code is available, tested)

AMBA总线的Verilog语言模型 包括:AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。