交通灯 通过测试 有测试文件

1）选择一个语音信号作为分析对象，或录制一段语音信号； 2）对语音信号进行采样，画出采样前后语音信号的时域波形和频谱图； 3）利用MATLAB中的随机函数产生噪声加入到语音信号中，使语音信号被污染，然后进行频谱分析； 4）设计用于处理该语音信号的数字滤波器，给出滤波器的性能指标，画出滤波器的频率响应； 5）对被噪声污染的语音信号进行滤波，画出滤波前后信号的时域波形和频谱，并对滤波前后的信号进行比较和分析； 6）回放各步骤的语音信号，给出相应处理程序及运行结果分析。(1) Select a voice signal as an analysis object, or record a voice signal 2) sampling the voice signal, draw the waveform and frequency spectrum of the time domain before and after sampling the speech signal 3) using the random function in MATLAB generated noise was added to the speech signal, the speech signal to be contaminated, and then spectrum analysis 4) for processing the speech signal, the digital filter design, given the performance of the filter to draw the filter' s frequency response 5) on the noise pollution of the speech signal is filtered, time-domain waveform and spectrum draw before and after filtering the signal before and after filtering, and the signal for comparison and analysis 6) playback of the speech signal for each step, given the results of the corresponding processing procedures and run analysis.)

利用实现verilog语言实现，pwm波的实现通过观察led灯的来实现，文件内附testbench文件

基于 FPGA的 VGA 接口的实例，在这里，我们先要考虑 vga_interface.v 支持的图像分辨率，亦即 16x 16 。所以 RAM 所需要的储存空间是 16Bits x 16Words。RAM 和 FIFO 一样，要访问 RAM 的时候都需 要拉高 xx_En_Sig 信号。由于RAM 包含 16Bits 所以 Write_Data 和 Read_Data, 皆 是16 位的位宽。当然，16Words 表示了 xx_Addr_Sig 是 4位的位宽。

虽然Loeffler DCT实现了良好的质量转换

嘿，这里是 ise 格式代码为 xilinx 软件 verilog 的 8 位固定点编码使用此编码与测试工作台为例

　　本文对数字基带信号脉冲成型滤波的应用、原理及实现进行了研究。首先介绍了数字成型滤波的应用意义并分析了模拟和数字两种硬件实现方法，接着介绍了成形滤波器设计所需要MATLAB软件，以及利用ISE system generator在FPGA上进行滤波器实现的优势。文中给出了成形滤波函数的数学模型，讨论了几种常用成形滤波函数的传输特性以及对传输系统信号误码率的影响。然后介绍了本次设计中使用到的数字成形滤波器设计的几种FIR滤波器结构。把各种设计方案进行仿真，比较仿真结果，最后根据实际应用的情况并结合设计仿真中出现的问题进行分析，得出各种设计结构的优缺点以及适合应用的场合。(In this paper, the application of the principles and implementation of digital baseband signal pulse shaping filter is studied. First introduced the significance of digital shaping filter application and analysis of both analog and digital hardware implementation, then introduces the shaping filter design requires MATLAB software, and the use of ISE system generator on the FPGA to achieve the advantages of the filter. This paper presents a mathematical model of shaping filter function, the transmission characteristics discussed several common shaping filter functions and the impact on the error rate of the signal transmission system. Then introduced the use of this design to several digital shaping filter design FIR filter structure. The various design simulation, compare the simulation results, and finally according to the actual application and combine design simulation to analyze problems, come and where appropriate to the application advantages and disadvantages of various design s)

数字钟电路的实现，可以24小时计时，可调整时间！(Digital clock circuit implementation, a 24-hour timer, adjustable time!)

jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)

module LDPC (clk,reset,             data_in, data_in_en,             velocity, /*输入信号码率选择*/             data_out, data_out_en,             indication /*输出信号，第一个127要删除前5成7488，指示第一个127*/                );input   clk,reset;input   data_in,data_in_en;input[1:0]  velocity; //码率选择信号output[126:0]   data_out;output  data_out_en;output  indication;

a big number class and a calculator using the class