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CPU-Verilog
说明: 简单流水线CPU,使用 verilog实现,实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)
- 2020-06-23 19:40:01下载
- 积分:1
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flash_test_24
实现fpga 读写flash 在k7上验证(Realization of FPGA read-write flash verification on K7)
- 2020-06-18 20:00:02下载
- 积分:1
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交织和解交织模块,采用矩阵交织方式,且有两套并行存储器,可以实现连续数据流操作,不会有数据滞留和丢失...
交织和解交织模块,采用矩阵交织方式,且有两套并行存储器,可以实现连续数据流操作,不会有数据滞留和丢失-Intertwined intertwined reconciliation module, interwoven matrix approach, and has two sets of parallel memory, you can realize continuous data stream operations, will not have data retention and loss
- 2022-01-30 11:03:35下载
- 积分:1
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USB2.0的VHDL描述,很经典了,欢迎大家下载
USB2.0的VHDL描述,很经典了,欢迎大家下载-USB2.0 the VHDL description, very classic, and welcomes everyone to download
- 2023-04-17 09:30:03下载
- 积分:1
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AD6 中进行FPGA设计与仿真
说明: AD6 中进行FPGA设计与仿真,很不错的资料哦(FPGA design and Simulation in AD6, very good data)
- 2020-04-15 21:22:17下载
- 积分:1
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liyuanlnx_IP_RAM
FPGA——IP_RAM实验:
创建IPRAM核,单端口,10位地址线(256字节),8位数据线(每字节8byte),读写使能
input [9:0] address;
input clock;
input [7:0] data;
input wren; //置1则写入
output [7:0] q;
LNXmode:控制LEDC显示
1:mode1,从k1~k3输入data的低4位,ledb计时,从0~f,计时跳变沿读取k1~k3的值,存入RAM
8个数之后,从RAM输出数据,用leda显示,同样每秒变化一次(The experiment of FPGA-IP_RAM:
Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)
- 2020-06-22 04:20:02下载
- 积分:1
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通过vhdl实现ls138硬件功能 通过vhdl实现ls138硬件功能
通过vhdl实现ls138硬件功能 通过vhdl实现ls138硬件功能 -the description of ls138 in vhdl
- 2022-07-14 19:56:28下载
- 积分:1
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test bench for alu 6 functions
test bench for alu 6 functions
- 2022-03-02 06:50:51下载
- 积分:1
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clock_gyc_system
基于用户自定义模块的实时时钟的设计;Qsys硬件设计;(Custom real-time clock module-based design Qsys hardware design )
- 2020-12-23 09:19:08下载
- 积分:1
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VendingMachine
VHDL Vendingmachine source
- 2013-11-02 06:19:46下载
- 积分:1