基于FPGA的DDR3控制器

modelsim下的60进制计数器源码和测试激励文件(modelsim M counter 60 under the source file and test incentives)

说明：  ds1302时钟驱动程序，已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)

实现任意倍数的倍频,帮助大家解决VHDL倍频问题,(The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,)

用于检测信号上升沿，输出与时钟相关的正脉冲(Detect the rising edge of the signal)

流水灯在Verilog语言下的分模块设计。分别是时钟脉冲+计数器+LED控制

This CAN Controller was tested with the Bosch VHDL Reference Model and passed all the tests. Because of the licensing issue it can not be published on the Opencores web site. The Can Controller was also implemented in real HW (12 boards were constantly talking to each other). The included test bench is not a real test bench and should be improved. However a volunteer is needed for such a job. I can provide some help but am not willing to write it by myself.

DEBOUNCEfpga的实现，运用软件实现数码管的变化(fpga of the)

说明：  xilinx SP6系列的3-8译码器实现(Implementation of Xilinx SP6 Series 3-8 Decoder)

FPGA控制DA（AD9740）的程序代码，包含mif文件，基于verilog编写，已调试通过。

一个1MHz的FIR低通滤波器。 ① 时钟信号频率16MHz; ② 输入信号位宽8bits，符号速率16MHz； ③ 要求在Matlab软件中进行FIR滤波器浮点和定点仿真，并确定FIR滤波器抽头系数； ④ 写出测试仿真程序。(A 1MHz FIR low pass filter. (1) The clock signal frequency is 16MHz; (2) The input signal has a bit width of 8 bits and a symbol rate of 16 MHz; (3) Floating-point and fixed-point simulation of FIR filter is required in Matlab software, and tap coefficients of FIR filter are determined. (4) Write the test simulation program.)