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基于FPGA的DDS
基于FPGA的DDS。可以产生三种波形:正弦,方波,三角波。频率分辨率0.012Hz。频率从0至25MHz任意可调。(FPGA-based DDS. Can produce three waveforms: sine, square, triangle wave. Frequency resolution 0.012Hz. Frequency is adjustable from 0 to 25MHz.)
- 2013-08-05 07:06:22下载
- 积分:1
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32位浮点乘法verilog HDL
它是基于Verilog硬件描述语言浮动乘法器的数字化设计。该设计可以实现全功能,是更好的灵活性,其理论基础上浮动计算并补偿位移倍增。
- 2023-01-22 04:10:03下载
- 积分:1
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cic_compensating
CIC 补偿滤波器。采用两种方法来设计,一个是frequency sampling method。另一个是Equal Rippler Design Method。这是一个非常有用的matlab代码。(CIC compensation filter. Two ways to design a frequency sampling method. The other is an Equal Rippler Design Method. This is a very useful matlab code.)
- 2012-10-17 14:22:08下载
- 积分:1
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Yoshis_Island_(V1.0)_(U)
Bringing SMW2:YI Back To LIFE Through Rom!
- 2013-01-19 23:40:42下载
- 积分:1
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SRIO-phy-code
SRIO接口物理层的实现代码,非常复杂,完全自己用verilog编写,支持5G速率,可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)
- 2020-10-01 11:57:42下载
- 积分:1
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基于FPGA的信号发生器20140506
说明: 基于FPGA的芯片信号发生器,利用Verilog语言实现信号发生器的各个模块单元,
实现的要求:正弦波、三角波、方波等;(Based on FPGA chip signal generator, using Verilog language to realize each module unit of the signal generator, Requirements: sine wave, triangle wave, square wave, etc;)
- 2019-12-30 11:48:26下载
- 积分:1
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SystemC-UART
基于SystemC的Uart模型-----文档(SystemC the Uart model of----- document)
- 2013-01-24 16:41:35下载
- 积分:1
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I2C
I2C verilog源代码实例并带有验证平台(iic source code and testbench)
- 2018-06-08 15:46:23下载
- 积分:1
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基于FPGA的串口通信
资源描述基于fpga的串口通信,采用verilog语言,实验开发板与pc机之间的串口通信
- 2022-03-12 20:42:57下载
- 积分:1
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Xilinx_2018_Licenses_Downloadly.ir
说明: Xilinx Licenses 2018
- 2020-06-25 08:20:01下载
- 积分:1