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UDP / IP上的Spartan3E以太网通信
UDP / IP上的Spartan3E以太网通信通过斯巴达3E发送UDP数据包到/从我的电脑。
- 2022-06-20 12:49:08下载
- 积分:1
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以前在学校里的课程设计,使用verilog编写的一个CPU程序,可以下板子...
以前在学校里的课程设计,使用verilog编写的一个CPU程序,可以下板子-Ago in the school curriculum design, the use of Verilog CPU prepare a procedure under the board
- 2022-01-20 22:48:37下载
- 积分:1
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altera的ip核,在sopcbuilder中添加后,在niosII IDE中可以用一条语句实现,音频解码的输出。...
altera的ip核,在sopcbuilder中添加后,在niosII IDE中可以用一条语句实现,音频解码的输出。-altera
- 2022-03-05 12:43:51下载
- 积分:1
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CPU-
五级流水线CPU实现(带Hazard),还没来得及实现Cache求高人指教(pipeline CPU with Hazard)
- 2020-12-03 12:59:24下载
- 积分:1
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5_ADC_Lab
基于altera公司MAX10型FPGA的ADC调试程序(ADC-based debugger altera company MAX 10 type of FPGA)
- 2015-11-18 10:56:16下载
- 积分:1
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design_pcie-based-on-FPGA
the interface design of pcie based on FPGA
- 2015-12-17 15:52:45下载
- 积分:1
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带FIFO的ov7670 FPGA应用程序,经测试可用
这是用Verilog编写的OV7670摄像头驱动代码,带FIFO,经测试可用。(This is written in Verilog OV7670 camera driver code, with FIFO, tested available.)
- 2021-04-08 21:19:00下载
- 积分:1
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sha1_v01
说明: SHA-1加密算法的IP核,内涵文档,仿真测试文件(SHA-1 encryption algorithm of the IP core, the connotation of documents, simulation test file)
- 2008-10-15 09:05:58下载
- 积分:1
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Shumaguan
在BASYS3上实现跑马灯的功能。第一LED交替闪烁;第二LED由左至右逐个变亮,再逐个变暗;第三LED由右至左逐个变亮,再逐个变暗;第四LED由两边逐个变亮,再从中间逐个变暗。(Realize the function of the horse light on BASYS3. The first LED flashes alternately; second LED brightens from left to right and then darkens one by one; the third LED turns from right to left, then darkens one by one, and then darkens one by one; fourth LED is brightened by both sides, and then darkening from the middle.)
- 2018-06-21 11:06:16下载
- 积分:1
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FPGA
说明: 基于FPGA的数字式相位测量仪的设计与制作(FPGA-Based Digital Phase Meter Design and Production)
- 2010-04-16 19:40:41下载
- 积分:1