从站设计在Altera的fpga上实现powerlink的从站设计

说明：  verilog讲义 卡内基梅陇大学verilog课程讲义-unlocked 卡内基梅陇大学verilog课程讲义-unlocked(Verilog Course Lectures at Carnegie Mellon, University Verilog Course Lectures at Carnegie Mellon University Verilog Course Lectures at Carnegie Mellon University)

有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的. 练习三 利用条件语句实现计数分频时序电路 实验目的： 1. 掌握条件语句在简单时序模块设计中的使用； 2. 学习在Verilog模块中应用计数器； 3. 学习测试模块的编写、综合和不同层次的仿真。 练习四 阻塞赋值与非阻塞赋值的区别 实验目的： 1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别； 2． 了解阻塞赋值与非阻塞赋值的不同使用场合； 3． 学习测试模块的编写、综合和不同层次的仿真。 -The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment usi

JOP字节码获取的源码，很重要，具体FPGA中实现-JOP byte code access to the source code is important to achieve specific FPGA

HDB3编码通过verilog实现，通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)

用VHDL语言编写的串口通讯模块，可以实现发送和接受功能。-A UART module writen in VHDL.

Fonts for LCD 162x64 (6x8)

几大代工厂的flash verilog源代码(flash verilog code)

CH341A的I2C接口Labview all vision (CH341A I2C Labview)

酷睿系列流水灯通用程序，来回往返流水，点亮led(ledwater for ep2c8q208c8)

AD9910实现脉冲内线性调频信号，仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)