从站设计在Altera的fpga上实现powerlink的从站设计

DW8051单片机的设计，用HDL设计，详细的HDL设计-DW8051 microcontroller design, HDL design, detailed design of the HDL

800 x 480 / inch lcd

基于FPGA的超声波测距，通过数码管显示距离(FPGA-based ultrasonic distance)

this a vhdl code for usb-this is a vhdl code for usb

基于VHDL语言的设计8位CISC微处理器实例-VHDL design language based on 8-bit CISC microprocessor examples

说明：  STM32F103 ADC 通过DMA进行读取(STM32F103 ADC reads by DMA)

Verilog 编写的IP核，512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM

This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.

vga，显示彩条，及其简单易懂，适合初学(vga, display color bars, and its easy-to-understand, suitable for beginners)

该程序用来实现电话计时以算取费用，比较简单(telephone cost metering verilog code)