一个UART协议验证

XAPP134 SDRAM VHDL design file

加性高斯白噪声生成的VERILOG实现，包含所有的testbench文件。可直接使用(Additive white gaussian noise generated VERILOG realized, including all testbench files. Can be used directly)

最大值求解是利用System Generator平台实现的比较方便不用自己写verilog代码就可以在Xilinx平台下使用，非常方便实用！

最新热血江湖外挂，需要的可以下载，游戏开心热血江湖应用辅助(Yulgang latest plug-in needed to download, games happy))

ad9361 matlab驱动代码，运行此代码可在matlab中控制AD9361(AD9361 matlab driver code, running this code can control AD9361 in MATLAB)

使用一个寄存器型参数来实现16位数据传完成后寄存器地址加1

dekoder code s Gray to cod „ 1 from 16”. This is program i VHDL

这个课程设计的题目是模拟电压采集电路路与程序设计,报告书的内容都比较详细. (The topics of this course design is an analog voltage acquisition circuit Road and program design, the contents of the report are more detailed.)

说明：  一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。(A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.)

数字化，宽带化，是当今无线通信的重点主流方向，FPGA以其功能强大，开发周期短，投资少，可重复修改，开发工具智能及软件可升级等特点成为无线通信首选。(Digital, broadband, is the focus of today s mainstream wireless communications, FPGA with its powerful, short development cycle, low investment, repeatable modify, intelligence and software development tools and other characteristics can be upgraded to become the first choice of wireless communication.)