温度传感器TMP121控制代码——Verilog

Routine for I2C in VHDL

Nonlinear discrete system identification, It uses a pulse of consumer law, Partial least squares method.

应用背景ADPLL数字锁相环在fpga上工程中有广泛的应用，程序有verilog语言编写关键技术全数字锁相环ADPLL由verilog HDL语言编写在FPGA上使用。

基于DB8小波变换的verilog代码设计，支持Avalon总线(Verilog DB8 Wavelet Transform Based on code design, support Avalon bus)

本白皮书探讨了在PCI Express的因素 技术可能会影响性能。它还 提供指导如何估算 的系统性能。(This white paper explores the factors in PCI Express technology may affect performance. It also provides guidance on how to estimate the system performance.)

PCI slave IP core, in VHDL language ,has been verified,it is very easy to use. it is an ideal IP to study PCI,design PCI Bridge

说明：  verilog 编写的I2C程序，控制D/A的(I2C program written by Verilog to control D/A)

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

Blessing_3_v3_9_6稳定盈利set，仅限AUDNZD货币对，周期M1。 使用本压缩包内的SET，LAF默认是15，根据历史测试来看具有较大的风险，需要手动规避数据。 合理设置为LAF=8，请自行设置和调试，找到自己合适的风险值。 (Blessing_3_v3_9_6 stable profit set, only AUDNZD currency pairs, cycle M1. Use this package in the SET, the default is 15 fans, according to the angles of history test has great risk, need to avoid data manually. Reasonable set to fans = 8, please make your own setting and debugging, find their proper risk value.)

这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)