DC_EX verilog 实现

完成GPS的IRIG_B码解码，已经模块化，并且有详细的中文注释(Completed the GPS IRIG_B of decoding modular, and there are detailed notes in Chinese)

实现多路可变时分复用，包括复接器，解复接，比特同步，帧同步，分频器(Implement multi-channel variable time division multiplexing, including multiplexer, demultiplexing, bit synchronization, frame synchronization, frequency divider)

fpga永磁同步电机矢量控制系统，包括死区等模块(fpga foc)

Cores are generated from Confluence a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C

。给出了时域滤波的基本原理以及通常采用的 IIR 椭圆地物杂波滤波器的设计方法。重点研究了回归滤波器这一时域滤波算 法。从正交多项式的拟合出发，给出了回归滤波器抑制地物杂波的基本原理及 其滤波实现过程。通过对回归滤波器的计算复杂度的研究，寻找使回归滤波器 计算量最小的正交多项式。分析了回归滤波器频率响应特性，比较了回归滤波 器与IIR 椭圆地物杂波滤波器的计算复杂度。利用仿真的雷达信号，分析了回 归滤波器的地物杂波抑制性能。回归滤波器实际上是一高通滤波器，它在滤掉 低频地物杂波的同时，对落在滤波器阻带内的天气回波信号同样会造成衰减。 在天气回波信号谱宽固定的情况下，通过改变天气回波信号的平均多普勒频率， 分析了回归滤波器对它的衰减情况。在基于一组实际采集的雷达信号的基础上， 给出了回归滤波器的地物杂波抑制比随着滤波器阶数的变化情况。(Firstly, this dissertation introduces the research background and significance of ground clutter suppression, analyzes the characteristics of the ground clutter and weather signals in the Doppler weather radars and simulates Doppler radar echo signals (It includes ground clutter, weather echo signals and the mixture of them). The simulated signals are used later to study the time and frequency domain ground clutter suppression. Secondly, this dissertation talks about the time domain filtering, gives the basic theory of time domain filtering and describes the design method of the usually used fifth-order elliptic infinite impulse response (IIR) ground clutter filter. In the time domain, the work focuses on the regression filter. From the orthogonal polynomials fit, this dissertation gives the basic theory of the regression filter for ground clutter suppression and the filtering process using a regression filter. Through the study of the computational complexity of regression)

使用DWT进行4级图像压缩使用DWT进行4级图像压缩使用DWT进行4级图像压缩使用DWT进行4级图像压缩使用DWT进行4级图像压缩使用DWT进行4级图像压缩使用DWT进行4级图像压缩使用DWT进行4级图像压缩

用Verilog语言编程实现4位BCD计数器的功能(Write the programm with Verilog language to implement the function of 4 - bit BCD counter.)

用FPGA实现 VGA显示的图像显示控制器设计 用VHDL实现 硬件实现是屏幕上面出现彩色条纹(VGA display with FPGA image display controller design Using VHDL hardware implementation is colored stripes appear above the screen)

SOPC技术的fpga的实现verilog硬件描述语言，编写的在niosII 程序   采用altera芯片

说明：  led学习控制l44444444444444(led verilog led ccccccc)