这是一个用vhdl语言实现的比较完整的ALU,可以用作其他cPU设计的部件...

开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit

国外的VHDL应用例子，大家可一好好参考一下！-abroad VHDL Application examples, we can make reference to a properly!

FPGA数字AGC(帮同学做的毕业设计)-FPGA digital AGC (help students to do the graduation project)

基于FPGA的利用rom进行查询的方式生成一个频率为10KHZ的sin信号，编译成功，并实现功能仿真。(Query based on the the FPGA use of rom generate a frequency of 10 kHz sin signal, compiled successfully and to achieve functional simulation.)

vmm log 验证平台，采用vmm搭建 (vmm log verification platform, built by vmm)

Mano s cpu for Man s instructions

DDS的VHDL程序，相当好，值得下载，共享才是王道(DDS, VHDL program is quite good, worth downloading, sharing is king)

VHDL 的100例程代码，能够使你熟练掌握VHDL语言的编写(100 routines of VHDL code, enabling you to master the preparation of the VHDL language)

SRAM 读写实验，SRAM存储器的读写操作，Verilog源码有助于提高代码coding能力。使用例程。(SRAM write and read)

MMC卡的VHDL源代码实现，经过大批量生产验证-MMC card VHDL source code to achieve, through large-scale production test