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CPLD_DEMO_OK
可以给VHDL初学者看的实例,全部经过验证(VHDL beginners can see examples of all the proven)
- 2011-01-12 21:09:45下载
- 积分:1
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zuoye2
主要编写了一组二进制数据通过根升余弦滤波器后的波形,但并没有使用ISE内部的FIR滤波器内核,该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)
- 2013-09-18 15:24:13下载
- 积分:1
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systemgendesignguide
这是使用systemgenerator的一个入门程序和范例使用matlab和system generator共同实现,并配有教学文档,清晰简单,易懂(This is an entry using systemgenerator procedures and examples using matlab and the system generator together to achieve, and with a teaching document, clear and simple and easy to understand)
- 2011-02-06 16:32:40下载
- 积分:1
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此示例是8051核加频率计的联合设计,带有8051IP核资料
此示例是8051核加频率计的联合设计,带有8051IP核资料-This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP
- 2022-06-14 22:57:42下载
- 积分:1
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AD
说明: FPGA实现的AD采样控制程序的源码,欢迎大家下载(FPGA implementation of the AD sampling control)
- 2021-04-14 21:18:55下载
- 积分:1
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build a music player with nios 2
build a music player with nios 2
- 2023-01-23 06:00:03下载
- 积分:1
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DES加密算法的VHDL实现,采用流水线技术实现
DES加密算法的VHDL实现,采用流水线技术实现(The VHDL implement of DES encrypt algorithmic)
- 2020-07-01 03:00:02下载
- 积分:1
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93 std
-- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn
- 2022-02-25 16:35:00下载
- 积分:1
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ALU_74181_me
学习ALU的设计方法。
2、用HDL语言采用行为描述的方法完成74181的逻辑设计 。(Learn the design method of ALU.
2, use HDL language to use behavioral description method to complete 74181 logical design.)
- 2020-11-11 16:19:44下载
- 积分:1
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bankorder
说明: 银行排队系统的VHDL程序实现,可以实现排队顾客自动取号,查看前面排队人数,银行服务柜台号等。(Bank queuing system VHDL program can be achieved automatically check its customers lined up to view the queue in front of the number of its banking services, such as counters.)
- 2008-11-28 15:49:49下载
- 积分:1