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sync-and-asyn_FIFO_verilog
同步与异步FIFO的verilog实现,包括源代码,testbench,测试以及综合通过,还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)
- 2021-03-07 14:19:29下载
- 积分:1
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ad7667.hdl
自己编写的AD7667的数据采集程序,因为之前没用过,首次写!
- 2022-02-28 09:44:00下载
- 积分:1
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本文介绍了使用verilog语言进行硬件设计的一些基本技巧
本文介绍了使用verilog语言进行硬件设计的一些基本技巧-This paper describes the use of Verilog hardware design language, the basic skills
- 2022-04-08 11:38:23下载
- 积分:1
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256字节深度的RS232串口程序,共分4个模块,顶层文件FIFO程序串口收和串口发.经过测试已用于产品.可靠!...
256字节深度的RS232串口程序,共分4个模块,顶层文件FIFO程序串口收和串口发.经过测试已用于产品.可靠!-Depth of 256-byte Serial RS232 procedures, divided into four modules, top-level document procedures FIFO serial and serial-fat collection. After the test has been used in products. Reliable!
- 2022-01-26 06:37:51下载
- 积分:1
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I2C主/从
用vhdl编写的主从式代码,会比较接近,它涉及i2c接口,主从式,每行都有注释,我建议如果你想对代码进行编辑就使用灵活的编辑器
- 2022-04-01 17:07:54下载
- 积分:1
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以太网控制器Verilog源码(含有MAC,MII接口)
以太网控制器Verilog源码(含有MAC,MII接口)(Ethernet controller Verilog source code (including MAC, MII interface))
- 2017-08-18 10:32:27下载
- 积分:1
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In the FPGA development board shows the string, using VHDL language, in a simple...
在FPGA开发板显示字符串,采用VHDL语言,以简单的功能说明FPGA的开发流程.-In the FPGA development board shows the string, using VHDL language, in a simple functional description FPGA-development process.
- 2022-03-25 05:15:56下载
- 积分:1
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一些较为经典的VHDL代码,专注于信号分析与检测方面
一些较为经典的VHDL代码,专注于信号分析与检测方面-Some of the more classic of the VHDL code, focusing on signal analysis and testing
- 2022-02-04 20:13:26下载
- 积分:1
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verilog-lfsr-master
Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.
- 2020-06-24 21:40:01下载
- 积分:1
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计数器,vhdl,调试通过。
COUNTER 用于xilinx硬件,里面已建工程,修改ucf即可。设计由3部分组成,计数器,100M分配时钟,顶层模块,其中顶层模块包括计数器和分频器。
- 2022-01-22 06:17:06下载
- 积分:1