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计数器的VHDL语言程序实现1
VHDL语言编写的计数器程序,实现1到9999计数,并动态扫描显示,带清零和暂停功能,课上作业自编程序-VHDL language of the counter program to achieve 1-9999 counts, and the dynamic scan showed, with Clear and suspension of functions, classes, on a self-compiled programs
- 2022-01-21 03:16:50下载
- 积分:1
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基于FPGA的DDS
基于FPGA的DDS。可以产生三种波形:正弦,方波,三角波。频率分辨率0.012Hz。频率从0至25MHz任意可调。(FPGA-based DDS. Can produce three waveforms: sine, square, triangle wave. Frequency resolution 0.012Hz. Frequency is adjustable from 0 to 25MHz.)
- 2013-08-05 07:06:22下载
- 积分:1
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课程设计-数字钟
说明: 具有计时 设置时间 闹钟 秒表 功能的数字钟设计 外设矩阵键盘(Digital clock design peripheral matrix keyboard with the function of timing setting time alarm clock stopwatch)
- 2020-05-18 17:11:07下载
- 积分:1
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multiplier
参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )
- 2011-12-08 15:14:04下载
- 积分:1
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使用LPM_ROM的实际的例子
使用LPM_ROM的实际的例子-Use of practical examples LPM_ROM
- 2022-10-03 13:00:03下载
- 积分:1
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bandpass
FIR有限冲击响应下带通滤波器的构建及滤波器仿真(通过matlab和simulink两种方法实现)(FIR finite impulse response bandpass filter and filter simulation (via two methods matlab and simulink))
- 2013-03-13 18:32:07下载
- 积分:1
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VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)
VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)
- 2022-01-25 18:25:54下载
- 积分:1
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HDB3modelsim
HDB3编码通过verilog实现,通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)
- 2020-06-18 05:20:02下载
- 积分:1
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自动打铃系统 附带时钟 定时打铃 整点打铃
自动打铃系统 附带时钟 定时打铃 整点打铃-Auto-play Ling System
- 2022-08-26 11:38:33下载
- 积分:1
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Ssmic13g_hs_nM
中芯国际130nm库文件,在DC综合练习中可以使用,并能帮帮助理解库的含义-DC Veriog,已通过测试。
(SMIC 130nm library file, you can use in the DC Comprehensive Exercises, and help to help understand the meaning of the library-DC Veriog has been tested.)
- 2012-07-19 20:25:03下载
- 积分:1