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verilog program for 8
verilog program for 8-bit multiplier
- 2023-07-15 11:05:03下载
- 积分:1
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clock
软件开发环境:ISE 7.1i 仿真环境:ModelSim SE 6.0 1. 多功能数字钟(Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock)
- 2009-03-22 12:44:34下载
- 积分:1
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NAND flash控制器VHDL代码
该资料为基于FPGA 的NAND flash控制器研究,语言为VHDL,代码已通过仿真验证
- 2022-01-25 21:00:37下载
- 积分:1
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nnpid
通过神经网络实现的PID算法,整个工程文件,调试通过。(By PID algorithm neural networks, the entire project files, debugging through.)
- 2020-11-20 21:39:37下载
- 积分:1
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CJQ-V1.0-fpga
实现FPGA对AD芯片AD7060的控制,程序代码的注释很多,易学易懂,适合初学者学习使用(it is good ...)
- 2013-10-10 11:20:31下载
- 积分:1
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第七次课--视频图像DCT处理及水印嵌入
熟悉IIC协议总线协议,采用IIC总线对图像采集传感器寄存器进行配置,并转换为RGB565格式。
利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
利用 SDRAM 接口模块的设计,实现了刷新、读写等操作;为提高SDRAM 的读写带宽,均采用突发连续读写数据方式;并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
利用双线性插值方法实现对图像640×480到1024×768的放大操作。
完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分:1
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Great guide for writing VHDL
Great guide for writing VHDL
- 2023-05-21 15:20:03下载
- 积分:1
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VGAPPS2PCORDIC
FPGA课程设计源码,整合VGA,PS2键盘,CORDIC三角函数算法,在basys2平台上使用完全可行。(FPGA curriculum design source, integrated VGA, PS2 keyboard, CORDIC trigonometric algorithm, used on basys2 platform entirely feasible.)
- 2015-10-12 20:56:05下载
- 积分:1
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THS1206
FPGA来实现数据采集,AD采用TI公司的THS1206,高速并行AD,内含16字FIFO,降低硬件复杂度。(FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.)
- 2009-07-09 09:08:27下载
- 积分:1
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Cordic_matlab
实现自然对数运算的cordic算法的matlab浮点仿真,以及针对FPGA硬件平台的定点仿真测试(Achieve natural logarithm of cordic algorithm matlab floating point emulation, and FPGA hardware platform for fixed-point simulation testing)
- 2013-11-01 15:10:09下载
- 积分:1