99记数VHDL的源程序,综合实验指导书上的,可以用的 大家下载哦...

多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)

verilog编写的SDRAM实验，有串口调试助手和相关资料！！！！！！！！！！！！！！！！！！！！！(Verilog prepared by the SDRAM experiment, a serial debugging assistant and related information!!!!!!!!!!!!!!!!!!!!!)

vga，显示彩条，及其简单易懂，适合初学(vga, display color bars, and its easy-to-understand, suitable for beginners)

这是一个经过测试和使用的VHDL代码，用于将16位二进制输入数据转换为4位BCD。如果您直接驱动显示器而不经过处理器，并且希望显示在主程序中计算的参数，则该程序非常有用。有关转换的戏剧方面，请阅读随附的pdf。

des code source vhdl sur fpga

数字式移相信号发生器可以产生预置频率的正弦信号，也可产生预置相位差的两路同频正弦信号，并能显示预置频率或相位差值；-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;

在VHDL结构体中用于描述逻辑功能和电路结构的语句分为顺序语句和并行语句两部分，顺序语句的执行方式十分类似于普通软件语言的程序执行方式，都是按照语句的前后排列方式顺序执行的。(VHDL structure in the body used to describe the logic function and circuit structure of the order of statements and expressions are divided into two parts in parallel statement, modalities for the implementation of the order of statement is very similar to ordinary language software program implementation, are in accordance with the statements before and after the arrangement of the order implementation.)

说明：  8位大小比较器的VHDL源代码，Magnitude Comparator VHDL description of a 4-bit magnitude comparator with expansion inputs(eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion)

quartus 17.1 安装包，我现在用的就是(Quartus 17.1 installation kit, what I am using now is)

CY7C63723 功能及其引脚描述，外围电路和仿真数据(The CY7C637 is an 8-bit RISC OTP microcontroller.)