-
运用vhdl程序设计语言进行ppm设计,ppm 设计在vhdl语言中非常常用,运用已经越来越广泛。...
运用vhdl程序设计语言进行ppm设计,ppm 设计在vhdl语言中非常常用,运用已经越来越广泛。-use vhdl program design language ppm design, vhdl ppm design in a very common language, has become increasingly widespread use.
- 2023-06-27 12:15:04下载
- 积分:1
-
verilogppt
北航夏宇闻的Verilog的PPT讲稿,挺经典的,适合初学者学习(Northern Xia Yu Wen' s Verilog the PPT script, very classic, suitable for beginners to learn)
- 2011-06-16 11:32:45下载
- 积分:1
-
base_4_fft
基4FFT原理及MATLAB实现,基本原理,编程思想等(base——4 FFT principle and MATLAB implementation, the basic principles of programming ideas, etc.)
- 2016-01-28 16:52:37下载
- 积分:1
-
spartanII 是xilinx公司提供的一款高性能FGPA芯片,本文详细介绍spartanII的体系结构和编程!...
spartanII 是xilinx公司提供的一款高性能FGPA芯片,本文详细介绍spartanII的体系结构和编程!-spartanII Xilinx is provided by a high-performance chip FGPA, spartanII This paper describes the architecture and programming!
- 2022-03-03 02:06:35下载
- 积分:1
-
usbd_ucos
说明: 基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41,基本实现了双向USB2.0 块传输(Bulk Transfer)通信,zynq的PS端接收USB数据并回传至主机。经测试,主机端Window10系统采用libUSBK编程时,采用64字节的块时,传输速率可达210Mbps。zynq开发工具为Vivado2015.4,程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)
- 2020-09-09 09:38:02下载
- 积分:1
-
Xilinx_2018_Licenses_Downloadly.ir
Xilinx Licenses 2018
- 2020-06-25 08:20:01下载
- 积分:1
-
VHDL Checkers Implementation
by
Ibrahim Elbouchikhi
Amir Nader
VHDL Checkers Implementation
by
Ibrahim Elbouchikhi
Amir Nader-Tehrani
-
VHDL Checkers Implementation
by
Ibrahim Elbouchikhi
Amir Nader-Tehrani
- 2022-06-13 17:00:51下载
- 积分:1
-
dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...
dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
- 2022-06-20 23:49:32下载
- 积分:1
-
基于FPGA的多路同步脉冲发生器设计1
说明: 采用FPGA(现场可编程门序列)编写VHDL语言设计多路同步脉冲发生器,对信号进行分频处理,实现四路信号相位相差T/16和T/8的延迟相位输出,实现的四路脉冲与传统的脉冲同步器不同,它具有高集成度,高通用性,容易调整和高可靠性等特点。(Using FPGA (field programmable gate sequence) to write VHDL language to design multi-channel synchronous pulse generator, to divide the frequency of the signal, to achieve the four-way signal phase difference T / 16 and T / 8 delay phase output, the realization of the four-way pulse is different from the traditional pulse synchronizer, it has the characteristics of high integration, high-throughput, easy adjustment and high reliability.)
- 2020-03-18 20:52:05下载
- 积分:1
-
textiowrite
quartus ii 环境下,一个完整的利用TEXTIO仿真的源代码,包括读数据文件和输出数据到文件。(Under quartus ii environment, a complete simulation using TEXTIO source code, including reading data files and output data to a file.)
- 2014-02-03 23:56:30下载
- 积分:1