CORDIC旋转

C++获取CPU占用率，一个类和一个头文件(Gets the CPU Use rate)

资源描述 modelsim输出文件代码演示 verilog  内含头文件和testbench.Verilog HDL是一种硬件描述语言（HDL:Hardware Description Language），以文本形式来描述数字系统硬件的结构和行为的语言，用它可以表示逻辑电路图、逻辑表达式。  

实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)

说明：  通过MATLAB产生单脉冲信号的数据，存储下来作为verilog代码实现的DDS的数据源，用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)

ad转换器ads822e/ads822的驱动模块(AD converter ads822e/ads822 driver module)

基于FPGA的AD和DA设计代码及文档(Design code and document of AD and DA based on FPGA)

该实验完成的功能是STM32与FPGA通信(The function of the experiment is STM32 and FPGA communication)

是codic算法实现atan的C程序，包括定点和浮点程序，已经通过验证。(Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.)

用Verilog代码实现的乒乓操作，用Verilog代码实现的乒乓操作(Verilog pingpong)

QPSK在赖斯信道下的模拟仿真，包括K=6和K=10下的情况(QPSK in, Laisi Xin Road, under the simulation, including the case of K = 6 and K = 10 under)