CPU 多周期

vhdl project at sbu uni in iran uart

通信IC设计的第二章Verilog参考学习代码，方便初学者学习入门，供学习参考用The codes of Chapter1 of《Communication IC Design》(The codes of Chapter2 of《Communication IC Design》)

数字时钟管理器，xilinx公司开发板集成时钟，实现分频、倍频等功能。(Digital clock managers, xilinx development board integrated clock divider, multiplier, and other functions.)

基于matlab的BOC仿真程序，包含BOSK调制等。(Based on the matlab the BOC simulation program, contains modulation BOSK.)

DDS波形生成器verilog语言书写（FPGA型号cy4以上）(DDS generate verilog)

多相滤波系统的设计与实现，有MATLAB仿真程序，有sysgen的系统仿真，还有VHDL代码，其中还有FIR的系数参数等等(Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on )

串口！ 这是一个使用的通信程序 ， 非常好用。(serial port Serial port! This is a communication program used, very useful.)

说明：  用于实现FPGA硬件开发使用的加法器，需要注意的是用Verilog语言实现的(The adder used to realize FPGA hardware development needs to be realized in Verilog language)

说明：  一个8位RiSC单片机的VHDL代码， 具有很好的参考价值。(an eight RiSC SCM VHDL code, is a good reference value.)

VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.